Renesas 8V19N49 Series Manual page 18

8V19N49x Hardware Design Guide
4.2.3.3 Receiver with Built-in Termination and DC Bias
This section provides a DC coupling termination interface example to shift down the DC offset level for 8V19N490
driver. In this example, the receiver has built-in termination and built-in DC bias of 0.5V. The DC offset is required
to shift close to this level.
VDDO
Figure 29. Interface to Receiver with Built-in Termination and Built-in DC Bias
The value of the component is shown in
VDDO = 3.3V. The QREF output is set to LVPECL style driver and the amplitude is set to 750mV.
R31UH0005EU0100 Rev.1.0
Jun 3, 2021
N490 QREF
LVPECL R1
R2
R5 R6 R3 R4
Table 4.
Table 4. Component Values
Component References
R1
R2
R3
R4
R5
R6
Figure 30. Simulation Waveform at the Receiver
0.5V
50 Ohm
IN
50 Ohm
VT
50 Ohm
50 Ohm
nIN
Component Values
100 Ohm
100 Ohm
100 Ohm
100 Ohm
200 Ohm
200 Ohm
Recevier
w ith Built-in
termination
and Built-in
Bias
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