Renesas 8V19N49 Series Manual page 12

8V19N49x Hardware Design Guide
Figure 14. Input Termination Example – 8V19N490 Reference Clock Input CLK/nCLK Driven by a 3.3V LVDS Driver
Figure 15. 8V19N490 Reference Clock Input CLK/nCLK AC Coupling Termination Example 1
Figure 16. 8V19N490 Reference Clock Input CLK/nCLK AC Coupling Termination Example 2
R31UH0005EU0100 Rev.1.0
Jun 3, 2021
VCC=3.3V
Zo = 50
Zo = 50
LVDS Driv er
Zo
Differential Signal
Zo
Zo
VCC=3.3V
R3
Differential Signal
R4
Zo
R1
100
VCC=3.3V
R3
R1
5.1K
5.1K
C1
R5
2 x Zo
C2 R2 R4
10K 10K
C1
R5
Zo
5.1K
10K
R5
Zo
C2
VCC=3.3V
CLK
nCLK
Clock Input
VCC=3.3V
CLK
nCLK
Clock Input
VCC=3.3V
CLK
nCLK
Clock Input
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