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8V19N49x Hardware Design
This document provides board-level hardware design guidelines for the 8V19N49x family products (see table).
The hardware design guidelines are similar for this product family. In this document, the 8V19N490 device is used
for demonstration purposes.
8V19N490, 8V19N490A, 8V19N490B, 8V19N492
8V19N490-24, 8V19N491-24
Contents
1.
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2.
Power Rails . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2.1
Bypass Capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2.2
Power Supply Isolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.
Loop Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.1
2nd Order Loop Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.2
3rd Order Loop Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.3
Loop Filter Calculation Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.3.1
Loop Filter for VCXO PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.3.2
Loop Filter for VCO PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.
Input Output Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.1
Input Termination for Reference Clock Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.2
Output Terminations for QCLK and QREF Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.2.1
LVPECL Type Driver Terminations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.2.2
LVDS Type Driver Terminations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.2.3
DC Coupling Interface for QREF Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.
Schematic Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
R31UH0005EU0100 Rev.1.0
Jun 3, 2021
Table 1. 8V19N49x Family
Part Number
8V19N490-19
8V19N491-36
8V19N492-39
VCO Frequency (GHz)
~2.94912
~1.966
~2.4576
~3.6864
~3.93216
© 2021 Renesas Electronics
Guide
Page 1
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Table of Contents
Related Manuals for Renesas 8V19N49 Series
Summary of Contents for Renesas 8V19N49 Series
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Page 1: Table Of Contents
Revision History ..............19 R31UH0005EU0100 Rev.1.0 Page 1 Jun 3, 2021 © 2021 Renesas Electronics... -
Page 2: Overview
8V19N49x Hardware Design Guide Overview As indicated, this document provides board-level hardware design guidelines for the 8V19N49x product family. The document also recommends power rail handling, loop filter calculation, and input/output termination. A general schematic example is shown in Figure 1. - Page 3 To minimize ESR between power pins and the bypass capacitors, Renesas suggests at least one bypass cap per power pin and to place these capacitors as close as possible to the power pins. Thicker trace widths between the bypass capacitor and power pin can also help reduce the ESR.
- Page 4 8V19N49x Hardware Design Guide Figure 4. Example of Larger Value (4.7uF) Bypass Capacitor Frequency Response Figure 5. Example of Smaller Value (100pF) Bypass Capacitor Frequency Response R31UH0005EU0100 Rev.1.0 Page 4 Jun 3, 2021...
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Page 5: Power Supply Isolation
8V19N49x Hardware Design Guide Power Supply Isolation Analog power rails require cleaner power to optimize the jitter performance of PLLs. Most parts in the N49x family contain built-in LDOs. An external ultra-low noise LDO may not be required but it is recommended for reducing power supply noise for noise-sensitive power lines such as VDD_LCF and the external VCXO. -
Page 6: 3Rd Order Loop Filter
8V19N49x Hardware Design Guide N is effective feedback divider. Fvco N Fvco is vco frequency. Fpd is the phase detector input frequency. 3. Calculate Cs. Where, α is ratio between loop bandwidth and the zero frequency at zero, α = fc / fz, recommend α to be greater than fz is frequency at zero. -
Page 7: Loop Filter Calculation Examples
8V19N49x Hardware Design Guide Charge Pump Driv er VCO Control Input Loop Filter Return Figure 7. Typical 3 Order Loop Filter The Rs, Cs, and Cp can be the actual value used in the 2 order loop filter. The following equation helps determine the 3 order loop filter R3 and C3. - Page 8 8V19N49x Hardware Design Guide VCXO-VC Figure 9. Typical 2 Order Loop Filter To calculate loop filter component values for loop bandwidth Fc = 40Hz with the reference CLK input frequency equals to 30.72MHz, set the input pre-divider Pv = 256. The phase detector input frequency Fpd = 0.12MHz. This satisfies the condition of Fpd / Fc >>...
- Page 9 8V19N49x Hardware Design Guide 3.3.1.2 Third Order Loop Filter for the VCXO PLL This section provides design guidelines for a 3rd order loop filter for the 8V19N490 VCXO PLL. A general 3 order loop filter is displayed in Figure VCXO-VC Figure 10.
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Page 10: Loop Filter For Vco Pll
8V19N49x Hardware Design Guide Table 2. Loop Filter Examples (Cont.) 51k Ohm 1.8k Ohm 4.7nF 33nF 1. Other VCXO frequencies can also be used with proper loop filter and parameter setting. Below are examples of VCXO order information: * 122.88MHz - Epson VG3225EFN 122.88M-CJHHBA * 245.76MHz - Epson VG3225ENN 245.76M-CJHHMA * 491.52MHz - Epson VG3225ENN 491.52M-CJGHSA 3.3.2... -
Page 11: Input Output Interface
8V19N49x Hardware Design Guide Table 3. VCO PLL 2 Order Loop Filter Recommendation VCXO used in the 1 122.88MHz 30.72MHz PDF, Phase detector input frequency 245.76MHz 61.44MHz with doubler on Feedback divider Suggest Charge pump current setting ~ 3.2ma (typical) ~3.2ma (typical) Suggest range setting Suggest range setting... - Page 12 8V19N49x Hardware Design Guide VCC=3.3V VCC=3.3V Zo = 50 nCLK Clock Input Zo = 50 LVDS Driv er Figure 14. Input Termination Example – 8V19N490 Reference Clock Input CLK/nCLK Driven by a 3.3V LVDS Driver VCC=3.3V VCC=3.3V 5.1K 5.1K Differential Signal 2 x Zo nCLK Clock Input...
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Page 13: Output Terminations For Qclk And Qref Drivers
8V19N49x Hardware Design Guide Output Terminations for QCLK and QREF Drivers The output stage of the 8V19N490 QCLK drivers can be configured to an LVPECL or LVDS style driver. 4.2.1 LVPECL Type Driver Terminations When the output is configured to an LVPECL style driver, the driver is open-emitter type and requires a pull-down resistor for the DC current path in order for the output to switch. - Page 14 8V19N49x Hardware Design Guide VCC=3.3V VCC=3.3V Zo = 50 nCLK High Input Impedance Zo = 50 LVPECL Driv er 0.1uF(optional) Figure 19. LVPECL 750mV Termination Example 2 VCC=3.3V VCC=3.3V LVPECL Driv er Zo = 50 50 Ohm 50 Ohm Zo = 50 120 to 240 120 to 240 8V79S680...
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Page 15: Lvds Type Driver Terminations
8V19N49x Hardware Design Guide 4.2.2 LVDS Type Driver Terminations An LVDS type driver does not require board-level pull-down resistors. A typical termination with DC coupling for an LVDS type driver is displayed in Figure 22. A termination with AC coupling example is shown in Figure VCC=3.3V VCC=3.3V... - Page 16 8V19N49x Hardware Design Guide 3.3V 3.3V 3.3V LVPECL Zo = 50 Zo = 50 3.3V or 2.5V LVDS R1//(R3+R5) = 50 ohm 3.3V*(R3+R5)/(R1+R3+R5) = 1.3V Figure 24. LVPECL 750mV to LVDS Receiver with High Input Impedance O S C IL L O S C O P E D e s ig n file : U N N A M E D 0 .
- Page 17 8V19N49x Hardware Design Guide 4.2.3.2 Receiver with Built-in Termination Figure 26 shows a receiver with built-in termination. The recommended termination for the non built-in is not feasible. The DC coupling interface example to shift down the DC offset level is displayed in Figure Figure 26.
- Page 18 8V19N49x Hardware Design Guide 4.2.3.3 Receiver with Built-in Termination and DC Bias This section provides a DC coupling termination interface example to shift down the DC offset level for 8V19N490 driver. In this example, the receiver has built-in termination and built-in DC bias of 0.5V. The DC offset is required to shift close to this level.
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Page 19: Schematic Diagrams
8V19N49x Hardware Design Guide Schematic Diagrams The following schematic diagrams are available from request: ▪ 8V19N490 EVB schematic ▪ 8V19N490 EVB board layout Revision History Revision Date Description Jun 3, 2021 Initial release. R31UH0005EU0100 Rev.1.0 Page 19 Jun 3, 2021... - Page 20 Renesas' products are provided only subject to Renesas' Terms and Conditions of Sale or other applicable terms agreed to in writing. No use of any Renesas resources expands or otherwise alters any applicable warranties or warranty disclaimers for these products.