Renesas 8V19N49 Series Manual page 8

8V19N49x Hardware Design Guide
LVF VCXO-VC
Rs
Cp
Cs
nd
Figure 9. Typical 2 Order Loop Filter
To calculate loop filter component values for loop bandwidth Fc = 40Hz with the reference CLK input frequency
equals to 30.72MHz, set the input pre-divider Pv = 256. The phase detector input frequency Fpd = 0.12MHz. This
satisfies the condition of Fpd / Fc >> 20.
The VCXO frequency Fvcxo = 122.88MHz, the effective feedback divider.
N = Mv = Fvcxo / Fpd = 1024
Rs can be calculated from the equation,
Rs = 33k ohm
Kvco VCO gain can be found or derived from the VCXO datasheet. The VCO gain can also be measured from lab
experiments. In this example, we use Kvco = 10kHz/V.
The 8V19N490 charge pump current can be programmed from 50uA to 1.6mA. In this example, assume the
charge pump current is programmed to Icp = 800uA.
Cs can be calculated from the following equation,
For α = 8, Cs is calculated to be 0.99uF. Cs greater than this value can be used to ensure that the α is greater than
12. For example, the actual chosen value can be 1uF from a standard capacitor value.
Cp can be calculated from the following equation,
For β = 4, Cp = 31nF. Less than this value can be used for Cp to assure that the β is greater than 4 (e.g., actual
chosen value Cp can be 27nF).
R31UH0005EU0100 Rev.1.0 Page 8
Jun 3, 2021