Lvds Type Driver Terminations; Dc Coupling Interface For Qref Driver - Renesas 8V19N49 Series Manual

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8V19N49x Hardware Design Guide
4.2.2

LVDS Type Driver Terminations

An LVDS type driver does not require board-level pull-down resistors. A typical termination with DC coupling for an
LVDS type driver is displayed in
VCC=3.3V
Figure 23. 8V19N490 LVDS Driver Driving a Receiver with Built-in Termination (e.g., 8V79S680/8V79S683
4.2.3

DC Coupling Interface for QREF Driver

The 8V19N49x QREF driver can be programmed to be an LVPECL or LVDS style driver. When programmed to an
LVPECL style driver, the output is an open-emitter type driver and can be terminated in a similar way as the
LVPECL termination (i.e., 50 Ohm to VTT or equivalence). When the QREF driver is programmed to an LVDS
style driver, the driver can be terminated as an LVDS driver (i.e., 100Ohm across). The output signals are not
quite same as standard LVPECL or LVDS. The amplitude can be programmed to different amplitude levels,
250mV, 500mV, 750mV, and 1000mV. The DC offset is about ~2V for both LVPECL and LVDS driver. 2V DC offset
is close the standard LVPECL signal; however, 8V19N490 LVDS DC offset is about 2V which is not standard. In
some applications, the receiver requires lower DC offset level with DC coupling interface. This section provides
several termination solution examples to shift down the DC offset to level using the DC coupling interface.
4.2.3.1
Receiver with High Input Impedance (No Built-in Termination)
Figure 24
shows an example of a DC coupling interface. In this example, the receiver is high-input impedance
without a built-in termination. The 8V19N490 driver is programmed to be an LVPECL style driver with 750mV
amplitude. The DC offset level is shifted down to approximately 1.2V and the amplitude is reduced to 400mV,
which is same signal of a standard LVDS level.
R31UH0005EU0100 Rev.1.0
Jun 3, 2021
Figure
22. A termination with AC coupling example is shown in
VCC=3.3V
Zo = 50
Zo = 50
LVDS Driv er
Figure 22. Typical LVDS Style Driver Termination
Zo
LVDS Driv er
C2
Zo
CLK/nCLK Input)
VCC=3.3V
CLK
R1
100
nCLK
C1
IN
VCC=3.3V
R3
5.1K
VT
R4
10K
nIN
Figure
Dif f erential Receiv er
VCC=3.3V
50 Ohm
50 Ohm
8V79S680
23.
Page 15

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