Hssp Timing Validation - Infineon PSoC 4 Quick Start Quide

PSoC 4 Programming Using an External Microcontroller (HSSP)

HSSP Timing Validation

7 HSSP Timing Validation
The host programmer must meet the timing specifications for the target device programming to achieve a
robust HSSP implementation. Those specifications are given in "Appendix D. Timing Specifications of the SWD
Interface" of the programming specifications document of the respective device listed in the
Documentation section.
The host programmer must meet the timing parameters specified for the SWD interface and programming
mode entry. To validate the timing, capture the SWDIO, SWDCK, and XRES signals on an oscilloscope. For power
cycle mode programming, the device power rails should be monitored instead of the XRES pin. Using the
captured waveforms, you can verify the timing parameters against the corresponding values provided in the
programming specification.
Application Note 19 of 45
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001-84858 Rev. *N
2021-03-23