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Infineon PSoC 6 Manual

Infineon PSoC 6 Manual

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AN219528
™
PSoC
6 MCU low-power modes and power
reduction techniques

About this document

Scope and purpose
™
AN219528 describes how to use PSoC
6 MCU power modes to optimize power consumption. Major topics
™
™
include low-power modes in PSoC
6 MCU devices, and power management techniques using PSoC
6 MCU
™
features. Associated code examples demonstrate different low-power techniques. See
AN230938 – PSoC
6 MCU
low- power analog
for additional information on the low-power analog peripherals of CY8C62x4 family devices.
More code examples? We heard you.
™
To access an ever-growing list of hundreds of PSoC
MCU code examples, please visit our
code examples web
page. You can also explore the video training library here.
Application note
Please read the sections "Important notice" and "Warnings" at the end of this document
002-19528 Rev. *E
www.infineon.com
2022-07-21

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  • Page 1: About This Document

    MCU code examples, please visit our code examples web page. You can also explore the video training library here. Application note Please read the sections "Important notice" and "Warnings" at the end of this document 002-19528 Rev. *E www.infineon.com 2022-07-21...

  • Page 2: Table Of Contents

    ™ PSoC 6 MCU low-power modes and power reduction techniques Table of contents Table of contents About this document ..............1 Table of contents .
  • Page 3 ™ PSoC 6 MCU low-power modes and power reduction techniques Table of contents 4.10 TCPWM ................32 4.11 SCB .

  • Page 4: Introduction

    ™ PSoC 6 MCU low-power modes and power reduction techniques 1 Introduction Introduction ™ PSoC 6 MCU gives the best power-saving benefit when low-power modes are implemented with other power-saving features and techniques, without significantly sacrificing the performance. This application note ™...

  • Page 5: Power Modes

    ™ PSoC 6 MCU low-power modes and power reduction techniques 2 Power modes Power modes Power mode transitions PSoC ™ 6 MCU features seven power modes that are divided into system modes that affect the whole device, ® and standard ARM CPU modes that affect only one CPU.
  • Page 6 ™ PSoC 6 MCU low-power modes and power reduction techniques 2 Power modes XRES/ XRES/POR/BOD XRES POR/BOD Deassert Assert System LP System ULP (0.9 V Core) (1.1 V Core) Firmware CPU active CPU active Firmware Action Action Firmware Peripheral Firmware Peripheral Action Interrupt...

  • Page 7: Cpu Sleep And Wakeup Instructions

    ™ PSoC 6 MCU low-power modes and power reduction techniques 2 Power modes CPU sleep and wakeup instructions ® Cortex ® CPUs transition between sleep and wakeup independently. Figure 2 shows several scenarios of wakeup from sleep. Wait-for-Interrupt ( ) is the core sleep instruction. After a CPU executes , the CPU goes to sleep and __WFI __WFI...

  • Page 8: Psoc ™ 6 Mcu Device Lpa Settings

    ™ PSoC 6 MCU low-power modes and power reduction techniques 2 Power modes ™ Figure 3 LPA software selection for PSoC Figure 4 Connectivity device LPA selection ™ 2.3.2 PSoC 6 MCU device LPA settings ™ Use the PSoC 6 MCU device section of the LPA to configure the initial power configuration of the device as shown in Figure 5.
  • Page 9 LPA software: Bluetooth power parameters ™ ® Infineon AIROC Wi-Fi & Bluetooth connectivity devices support a wide range of power optimization techniques that you can configure based on the needs of the application and network features supported, as shown in Figure 7.
  • Page 10 ™ PSoC 6 MCU low-power modes and power reduction techniques 2 Power modes Figure 7 LPA software: Wi-Fi power parameters Application note 002-19528 Rev. *E 2022-07-21...

  • Page 11: Subsystem Availability And Power Consumption

    ™ PSoC 6 MCU low-power modes and power reduction techniques 2 Power modes Subsystem availability and power consumption 2.4.1 Subsystem availability Each subsystem resource works differently in various system power modes. For example, the CPU can be in ON, OFF, and Retention modes. It is important to select proper peripherals for the power mode to work correctly. Table 2 lists the resources available in different power modes.

  • Page 12: Example Case Scenarios

    ™ PSoC 6 MCU low-power modes and power reduction techniques 2 Power modes Example case scenarios Proper power mode selection reduces power consumption without performance degradation. Table 2 lists sample scenarios of power modes. In some examples, only a few power modes are used effectively. Table 2 Sample case scenarios of power modes Power modes...

  • Page 13: System Power Management (Syspm) Library

    ™ PSoC 6 MCU low-power modes and power reduction techniques 2 Power modes System power management (SysPm) library 2.6.1 Overview The peripheral driver library (PDL) is a complete software tool that includes APIs for configuring peripherals and system registers to implement the desired functionality. PDL provides direct access to almost all hardware resources of the target device.
  • Page 14 ™ PSoC 6 MCU low-power modes and power reduction techniques 2 Power modes Figure 9 Power mode callback registration and deregistration By calling the mode transition function, the device starts to transition with four callback operations. The CPU ® sleep and CPU deep sleep modes use Arm sleep instructions.
  • Page 15 ™ PSoC 6 MCU low-power modes and power reduction techniques 2 Power modes In the system LP and system ULP modes, all system resources keep running. Entering system LP and ULP modes is done by configuring the power mode control register; the transition occurs without delay. SysPm PDL provides the associated driver functions, as shown in Figure 11.

  • Page 16: Psoc ™ 6 Mcu Power Management

    ™ PSoC 6 MCU low-power modes and power reduction techniques ™ 3 PSoC 6 MCU power management ™ PSoC 6 MCU power management Core voltage selection 3.1.1 Linear regulator and buck regulator ™ PSoC 6 MCU supports multiple on-chip regulators including low drop out (LDO) and single input multiple output (SIMO), or single input single output (SISO) buck to generate VCC for core power, as listed in Table The LDO can provide up to 300 mA in high-current mode (normal) and 25 mA in low-current mode.

  • Page 17: Ulp Mode Clock

    ™ PSoC 6 MCU low-power modes and power reduction techniques ™ 3 PSoC 6 MCU power management ULP mode clock Transition to ULP mode can be done by configuring the power mode control register. There is a maximum clock speed limitation in ULP mode as described earlier, so the clock configuration should be adjusted based on the regulator output when entering or exiting ULP mode.

  • Page 18: Backup Power Domain

    ™ PSoC 6 MCU low-power modes and power reduction techniques ™ 3 PSoC 6 MCU power management Backup power domain The backup domain is not a power mode but rather an always on group of resources that can be active during any of the device power modes.
  • Page 19 ™ PSoC 6 MCU low-power modes and power reduction techniques ™ 3 PSoC 6 MCU power management ™ directly connected to V – When the backup domain is only used with the full PSoC 6 MCU BACKUP device, there is no reason for a separate supply. V and V supply pins must be directly connected BACKUP...
  • Page 20 ™ PSoC 6 MCU low-power modes and power reduction techniques ™ 3 PSoC 6 MCU power management Figure 15 Backup domain supercapacitor connection Backup domain battery connection powered by battery – Figure 16 demonstrates a battery-powered V . When a battery BACKUP BACKUP supplies V...
  • Page 21 ™ PSoC 6 MCU low-power modes and power reduction techniques ™ 3 PSoC 6 MCU power management Figure 16 Backup domain battery connection powered by system provided supply – If an always-on power supply is already present in the BACKUP system, it can be used as the V supply BACKUP...

  • Page 22: Backup Domain Reset

    ™ PSoC 6 MCU low-power modes and power reduction techniques ™ 3 PSoC 6 MCU power management 3.3.2 Backup domain reset The backup domain is not reset by power-on reset (POR), brownout detect (BOD), watchdog timer (WDT), and external reset (XRES) events as long as V or V is present.
  • Page 23 ™ PSoC 6 MCU low-power modes and power reduction techniques ™ 3 PSoC 6 MCU power management Figure 17 PMIC controller interface To avoid errant code from disabling the PMIC controller, an unlock key is required before any other register writes.

  • Page 24: Wakeup Sources

    ™ PSoC 6 MCU low-power modes and power reduction techniques ™ 3 PSoC 6 MCU power management There are many options other than a direct connection to a dedicated PMIC. This flexibility allows optimizing power switching to the needs of the design. Some of the common pmic_wakeup_out pin connections are as follows: Advanced PMIC device providing multiple supply rails to V , and V...

  • Page 25: Backup Data Registers

    ™ PSoC 6 MCU low-power modes and power reduction techniques ™ 3 PSoC 6 MCU power management 3.3.5 Backup data registers The backup domain includes sixteen 32-bit registers, BACKUP_BREG[15:0], that retain their contents as long as the V supply is valid. Each register holds 4 bytes of data for a total of 64 bytes. These registers are used BACKUP to retain important system information and flags during power down of the full device.

  • Page 26: Other Power Saving Techniques

    ™ PSoC 6 MCU low-power modes and power reduction techniques 4 Other power saving techniques Other power saving techniques ™ Use PSoC 6 MCU to gate current paths Your PCB may contain other components that draw power; PSoC ™ 6 MCUs can be used to control the power through them by supplying the power with GPIO pins that can be turned ON and OFF in firmware.

  • Page 27: Disable Unused Blocks

    ™ PSoC 6 MCU low-power modes and power reduction techniques 4 Other power saving techniques Figure 20 Using a GPIO as a ground switch Disable unused blocks You can save unnecessary current consumption by disabling unused blocks. The power saved depends on the block disabled.

  • Page 28: Disabling Cpus

    ™ PSoC 6 MCU low-power modes and power reduction techniques 4 Other power saving techniques • System deep sleep • Power OFF with an external PMIC Disabling CPUs If the CM4 CPU is not used in the application, disable it by calling the function from the Cy_SysDisableCM4() CM0+ firmware.

  • Page 29: Clocks

    ™ PSoC 6 MCU low-power modes and power reduction techniques 4 Other power saving techniques Clocks In some cases, running CPU clocks faster can result in a lower average current consumption. For example, consider a design that takes a reading from a sensor once every second, performs several calculations, and then transmits the results to another device.
  • Page 30 ™ PSoC 6 MCU low-power modes and power reduction techniques 4 Other power saving techniques Figure 22 Analysis of tasks in CPU active mode at 8 MHz The time required for some tasks does not change even if the system clock frequency increases. Sensor reading and data transmitting fall into this category.

  • Page 31: Gpios

    ™ PSoC 6 MCU low-power modes and power reduction techniques 4 Other power saving techniques Figure 23 Analysis of tasks in active mode at 48 MHz Figure 24 Example current profile with 48 MHz clocks GPIOs ™ GPIOs can continue to drive external circuitry while the PSoC device is in any low-power mode.

  • Page 32: Sram

    ™ PSoC 6 MCU low-power modes and power reduction techniques 4 Other power saving techniques You should analyze your design and determine the best state for your GPIOs during low-power operation. If holding a digital output pin at logic ‘1’ or ‘0’ results in the lowest current, match that digital level using Cy_GPIO_Write() /* Set MyPin to ‘0’...

  • Page 33: Scb

    ™ PSoC 6 MCU low-power modes and power reduction techniques 4 Other power saving techniques clock is mostly linear based on clock frequency. TCPWM operating current at 100 MHz = 540 µA (SID.TCPWM.2B) while at 8 MHz = 70 µA (SID.TCPWM.1) per the CY8C61x6 datasheet. The same idea applies when using a PWM to dim an LED.

  • Page 34: Audio Subsystem

    ™ PSoC 6 MCU low-power modes and power reduction techniques 4 Other power saving techniques Figure 26 Example of blocking and non-blocking functions Instead of using the SCB interrupt to access its FIFO in firmware, use DMAs controlled by the FIFO level to reduce the amount of CPU cycles required in the application;...

  • Page 35: Usb

    ™ PSoC 6 MCU low-power modes and power reduction techniques 4 Other power saving techniques If the accuracy of the frame rates is not important for the application, do not use the ECO and/or PLL. For example, if your application implements a sound detector and can tolerate a higher error, use the FLL as the source for the audio subsystem.

  • Page 36: Voltage Dac

    ™ PSoC 6 MCU low-power modes and power reduction techniques 4 Other power saving techniques 4.16 Voltage DAC If the DAC voltage output needs to be periodically changed with pre-determined values, use a DMA to update the voltage value. This avoids using CPU cycles to write to DAC registers. If the external device that requires the DAC output voltage is used only periodically, keep the DAC disabled when its output is not required.

  • Page 37: Power Measurement

    ™ PSoC 6 MCU low-power modes and power reduction techniques 5 Power measurement Power measurement Measuring the current with a DMM When using a digital multimeter (DMM) to measure device current, it is important to know the value of the shunt resistor in the DMM.

  • Page 38: Power Supply Protection System

    ™ PSoC 6 MCU low-power modes and power reduction techniques 6 Power supply protection system Power supply protection system Hardware control 6.1.1 Brownout detect (BOD) Brownout detect (BOD) can reset the system before the logic state is lost when V and V power are lost.

  • Page 39: Summary

    ™ PSoC 6 MCU low-power modes and power reduction techniques 7 Summary Summary ™ Many power managing options can be used in PSoC 6 MCU. By following proper methods, you can optimize ™ your design and ensure that the power modes and features of PSoC 6 MCU give the best options for the lowest power consumption without degrading the required performance of battery powered devices.

  • Page 40: A Power Modes Summary

    ™ PSoC 6 MCU low-power modes and power reduction techniques A Power modes summary Power modes summary Power modes and wakeup source Table 5 Power modes and wakeup source System Description Entry conditions Wakeup Wakeup power power sources action mode mode Active Primary mode of operation.
  • Page 41 ™ PSoC 6 MCU low-power modes and power reduction techniques A Power modes summary Table 5 (continued) Power modes and wakeup source System Description Entry conditions Wakeup Wakeup power power sources action mode mode Sleep 0.9 V core voltage. One or more In system ULP mode, Any interrupt to Interrupt...

  • Page 42: Subsystem Availability

    ™ PSoC 6 MCU low-power modes and power reduction techniques B Subsystem availability Subsystem availability Resources available in different power modes Table 6 shows information for the resource availability in different power modes. Table 6 Resources available in different power modes Component System power modes Deep sleep Hibernate XRES Power off with...
  • Page 43 ™ PSoC 6 MCU low-power modes and power reduction techniques B Subsystem availability Table 6 (continued) Resources available in different power modes Component System power modes Deep sleep Hibernate XRES Power off with backup CPU active CPU sleep/ deep sleep active sleep/ deep...

  • Page 44: C Callback Function Examples

    ™ PSoC 6 MCU low-power modes and power reduction techniques C Callback function examples Callback function examples Register callback functions cy_stc_syspm_callback_params_t myParams; cy_stc_syspm_callback_t myAppSleep &Application_Callback, /* Callback function */ CY_SYSPM_SLEEP, /* Select Power Mode */ CY_SYSPM_SKIP_CHECK_READY CY_SYSPM_SKIP_CHECK_FAIL), /* Skip CHECK_READY and CHECK FAIL */ &myParams, /* Operation, contexts */ NULL,...

  • Page 45: Implement Custom Callback Functions

    ™ PSoC 6 MCU low-power modes and power reduction techniques C Callback function examples Implement custom callback functions cy_en_syspm_status_t Application_Callback( cy_stc_syspm_callback_params_t *callbackParams) cy_en_syspm_status_t retVal CY_SYSPM_SUCCESS; switch(callbackParams->mode) case CY_SYSPM_CHECK_READY: if(Check_HW()) /* Hardware is ready */ else retval CY_SYSPM_FAIL; break; case CY_SYSPM_CHECK_FAIL: /* Rollback any configuration during CHECK_READY */ Rollback_HW();...

  • Page 46: Code Examples

    ™ PSoC 6 MCU low-power modes and power reduction techniques D Code examples Code examples ™ CE219881 - PSoC 6 MCU switching between power modes This code example shows how to enter and exit system LP and ULP power modes and transition the CPU from CPU active to sleep or deep sleep.

  • Page 47: Ce218542 - Psoc

    ™ PSoC 6 MCU low-power modes and power reduction techniques D Code examples Figure 28 Wakeup from system hibernate mode using LPComp input ™ CE218542 - PSoC 6 MCU custom tick timer using RTC alarm interrupt This code example demonstrates how to configure the RTC registers for a periodic alarm interrupt using the PDL RTC driver API.

  • Page 48: Ce226306 - Psoc

    ™ PSoC 6 MCU low-power modes and power reduction techniques D Code examples Figure 29 RTC periodic wakeup timer using alarm interrupt ™ CE226306 - PSoC 6 MCU power measurements ™ This example shows how to configure PSoC 6 MCU devices to run the clock frequencies and system modes ™...
  • Page 49 ™ PSoC 6 MCU low-power modes and power reduction techniques D Code examples Table 7 Configuration options Configuration Options Description System mode SYSTEM_LP Defines the system mode the firmware enters – system low-power or system ultra-low-power modes. The following functions are used: SYSTEM_ULP Cy_SysPm_SystemEnterLp();...
  • Page 50 ™ PSoC 6 MCU low-power modes and power reduction techniques D Code examples Table 7 (continued) Configuration options Configuration Options Description CM0+ CPU mode CM0P_WHILE_L Defines what the CM0+ CPU runs – While (1) loop, Dhrystone algorithm, go to CPU sleep, go to CPU deep sleep or hibernate CM0P_DHRYST The same functions from the CM4 CPU Mode are used.

  • Page 51: References

    ™ PSoC 6 MCU low-power modes and power reduction techniques 12 References References Application notes ™ AN215656 – PSoC 6 MCU dual-CPU system design ™ ™ ® AN227910 – PSoC 6 MCU low- power system design with AIROC CYW43012 Wi-Fi & Bluetooth combo ™...

  • Page 52: Revision History

    ™ PSoC 6 MCU low-power modes and power reduction techniques Revision history Revision history Document Date of release Description of changes version 2017-09-12 New application note. 2018-05-05 Updated power mode names to match TRM names; CPU active, CPU, sleep, CPU deep sleep, system LP, system ULP, system deep sleep, system hibernate.

  • Page 53: Disclaimer

    Infineon Technologies, All Rights Reserved. information given herein in the real application. Infineon Technologies’ products may not be used in Infineon Technologies hereby disclaims any and all any applications where a failure of the product or warranties and liabilities of any kind (including without...

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