Infineon PSoC 4 Quick Start Quide page 9

PSoC 4 Programming Using an External Microcontroller (HSSP)
HSSP Firmware Architecture
This function returns the status byte. Use the status byte to infer error details from the bit field definitions.
See Figure 2 for the bit fields returned by this function.
Transition Error
Bit 7
Figure 2 HSSP Error Status Register
Table 6 describes the bit field definitions of this status register.
Table 6 HSSP Error Status Register
Bit Field Name
[2:0] SWD ACK
3 SWD Read Data Parity
Error
4 Port Acquire Timeout
5 SROM Polling Timeout
6 Verification Failure
7. Transition Error
To learn more about this register and for a detailed explanation of the bit fields, see
Definitions of HSSP Error Status Register.
Application Note
SROM Polling Timeout
Bit 6 Bit 5
Verification Failure Port Acquire Timeout
Description
These three bits store the acknowledge response of previous SWD
transactions.
If this bit is set, it indicates a parity error in the data received by the host.
If this bit is set, it indicates that the device was not acquired within the
timeout window.
If this bit is set, It indicates that SROM operations exceed 1 second.
This bit is set in multiple steps. Depending upon the step where failure
occurred, the reason can be inferred.
If this bit is set, it indicates that the chip protection settings read from the
chip and the hex file indicates a wrong transition.
SWD Read Data
Parity Error
Bit 4 Bit 3 Bit 2
SWD ACK [2:0] response
9 of 45
Bit 1 Bit 0
Appendix C: Bit Field
001-84858 Rev. *N
2021-03-23