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PSoC 4 Programming Using an External Microcontroller (HSSP)
HSSP Firmware Architecture
2
HSSP Firmware Architecture
HSSP for the target device is implemented in multiple layers using modular C code. These layers are as follows:
SWD Protocol Physical layer
1.
SWD Protocol Packet layer
2.
HSSP Programming Steps layer
3.
See
Figure 1
for the flow of control among these layers.
Note:
See the A_Hssp_Programmer project, which uses PSoC 5LP as the external host programmer,
attached with this application note for the implementation of this firmware.
HSSP Implementation Flow
Device Acquire
1.
2.
Verify Silicon ID
Erase all Flash
3.
4.
Checksum Privileged Calculation
5.
Program Flash
6.
Verify Flash
7.
Program Protection Settings
8.
Verify Protection Settings
9.
Verify Checksum
10.
Exit HSSP Programming mode
(1)
For power cycle mode programming, device power rails need to be
toggled instead of the reset (XRES) pin
Figure 1
HSSP Firmware Architecture
The HSSP Programming Steps layer uses the "Fetching Programming Data" interface to extract the
programming data from the source of the data (for example, the hex file data provided by any communication
interface—I
C, SPI, UART, or USB or host flash—as
2
layer uses the HSSP Timeout Parameters interface to configure timeouts in its programming APIs.
Application Note
Main application code
main.c
HSSP Programming Steps
ProgrammingSteps.h,
ProgrammingSteps.c
SWD Protocol Packet Layer
SWD_PacketLayer.h,
SwdPacketLayer.c
SWD_UpperPacketLayer.h,
Swd_UpperPacketLayer.c
SWD Protocol Physical Layer
RegisterDefines.h,
SWD_PhysicalLayer.h,
SWD_PhysicalLayer.c
SWDIO
Target PSoC 4
SWDCK
(1)
XRES
Figure 1
shows. In addition, the "HSSP Programming Step"
5 of 45
Host Programmer
Fetching Programming
Data
DataFetch.h,
DataFetch.c
HSSP Timeout
Parameters
Timeout.h,
Timeout.c
device
Programming
Data
HexImage.h,
HexImage.c
001-84858 Rev. *N
2021-03-23
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