Page 1 PSoC™ 6 MCU device hardware. Intended audience This document is intended for anyone who use the PSoC™ 6 MCU device. Reference manual Please read the Important Notice and Warnings at the end of this document 002-18176 Rev. *K www.infineon.com page 1 2023-07-26...
Page 2 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Table of contents Table of contents About this document Scope and purpose Intended audience Table of contents Section A: Overview Introduction ..............16 Features .
Page 3 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Table of contents Architecture ................49 7.2.1 Fault report .
Page 4 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Table of contents 9.7.6 Protection structure types ..............86 DMA controller .
Page 5 Infineon ID ........
Page 6 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Table of contents 14.2.5 SWD/JTAG repurposing ..............200 14.2.6 Waking up from hibernate .
Page 7 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Table of contents 18.5 Register list ................240 Backup system .
Page 8 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Table of contents 21.2.1 Power-on reset ................270 21.2.2 Brownout reset .
Page 9 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Table of contents 24.2 Architecture ................314 24.2.1 Trigger multiplexer group .
Page 10 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Table of contents 26.5.6 I2C buffer modes ................373 26.5.7 Clocking and oversampling .
Page 11 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Table of contents 29.3 Digital audio interface formats ............. . 453 29.3.1 Standard I2S format .
Page 12 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Table of contents 31.6 USB device registers ............... 493 Universal Serial Bus (USB) host .
Page 13 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Table of contents 34.3.6 PA reset multiplexer ............... 577 Section E: Analog subsystem Analog reference block .
Page 14 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Table of contents 39.2.4 SARSEQ ................. . 623 39.2.5 SAR interrupts .
Page 15 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Overview Section A: Overview This section encompasses the following chapters: • “Introduction” on page 16 • “Getting started” on page 20 • “Document organization and conventions” on page 21 Reference manual 002-18176 Rev.
Page 16 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Introduction Introduction This PSoC™ 6 MCU reference manual provides comprehensive and detailed information about the functions of the PSoC™ 6 MCU device hardware. It is divided into two books: architecture reference manual and registers reference manual.
Page 17 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Introduction Flexible clocking options • On-chip crystal oscillators • Phase-locked loop (PLL) for multiplying clock frequency • Internal main oscillator (IMO) • Ultra-low-power internal low-speed oscillator (ILO) • Frequency locked loop (FLL) for multiplying IMO frequency Quad-SPI (QSPI)/serial memory interface (SMIF) •...
Page 18 Usable as drag-and-drop Boolean primitives (gates, registers), or as Verilog programmable blocks • Infineon-provided peripheral component library using UDBs to implement functions such as Communication peripherals (for example, LIN, UART, SPI, I C, S/PDIF, and other protocols), Waveform Generators, Pseudo- Random Sequence (PRS) generation, and many other functions.
Page 19 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Introduction Architecture Figure 1-1 shows the major components of the PSoC™ 6 MCU architecture. PSoC™ 63 MCU with Bluetooth® LE CY8C63x6, CY8C63x7 Programmable Analog SAR ADC 12 bit Color Key: System Resources Power Modes and DAC 12 bit Domains...
Page 20 PSoC™ 6 MCU resources This chapter provides the complete list of PSoC™ 6 MCU resources that helps you get started with the device and design your applications with them. If you are new to PSoC™, Infineon provides a wealth of data at www.infineon.com to help you to select the right PSoC™...
Page 21 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Document organization and conventions Document organization and conventions This document includes the following sections: • “CPU subsystem” on page 29 • “System resources subsystem (SRSS)” on page 217 • “Digital subsystem” on page 327 •...
Page 22 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Document organization and conventions Table 3-1. Units of measure (continued) Abbreviation Unit of measure femtofarads Giga Hertz kilo, 1000 kilo, 2^10 1024 bytes, or approximately one thousand bytes Kbit 1024 bits kilohertz (32.000) k...
Page 23 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Document organization and conventions Table 3-2. Acronyms and initializations (continued) Acronym Definition Advanced Encryption Standard AMBA (advanced microcontroller bus architecture) high-performance bus, an Arm® data transfer bus application programming interface APOR analog power-on reset broadcast clock binary coded decimal...
Page 24 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Document organization and conventions Table 3-2. Acronyms and initializations (continued) Acronym Definition Data Encryption Standard D flip-flop digital or data input drive level direct memory access DMIPS Dhrystone million instructions per second differential nonlinearity digital or data output digital system interconnect...
Page 25 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Document organization and conventions Table 3-2. Acronyms and initializations (continued) Acronym Definition I/O read I/O write inter-processor communication IPTAT proportional to absolute temperature IRES initial power on reset interrupt request acknowledge identity resolution key interrupt request instruction set architecture...
Page 26 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Document organization and conventions Table 3-2. Acronyms and initializations (continued) Acronym Definition main stack pointer micro trace buffer next instant non-maskable interrupt NVIC nested vectored interrupt controller output enable over-sampling ratio over-voltage protection power amplifier program counter...
Page 27 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Document organization and conventions Table 3-2. Acronyms and initializations (continued) Acronym Definition resolvable private address root mean square read/write successive approximation register SARSEQ SAR sequencer LCD segment signal single-ended zero switched capacitor serial communication block SHA-256 Secure Hash Algorithm...
Page 28 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Document organization and conventions Table 3-2. Acronyms and initializations (continued) Acronym Definition TPIU trace port interface unit TRNG True random number generator UART universal asynchronous receiver/transmitter system ultra low-power mode universal digital block universal serial bus USBIO USB I/O...
Page 29 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture CPU subsystem Section B: CPU subsystem This section encompasses the following chapters: • “CPU subsystem (CPUSS)” on page 30 • “SRAM controller” on page 38 • “Inter-processor communication” on page 41 •...
Page 30 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture CPU subsystem (CPUSS) CPU subsystem (CPUSS) This PSoC™ 6 MCU reference manual provides comprehensive and detailed information about the functions of the PSoC™ 6 MCU device hardware. It is divided into two books: architecture reference manual and registers reference manual.
Page 31 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture CPU subsystem (CPUSS) Architecture CPU Subsystem Cortex® M4F CPU 150/50 MHz, 1.1/0.9 V SWJ, ETM, ITM, CTI Cortex® M0+ CPU 100/25 MHz, 1.1/0.9 V SWJ, MTB, CTI 2x DMA Controller Crypto DES/TDES, AES, SHA, CRC, TRNG, RSA/ECC Accelerator...
Page 32 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture CPU subsystem (CPUSS) 4.2.1 Address and memory maps Both CPUs have a fixed address map, with shared access to memory and peripherals. The 32-bit (4 GB) address space is divided into the regions shown in Table 4-1.
Page 33 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture CPU subsystem (CPUSS) 4.2.1.1 Wait state lookup tables The wait state lookup tables show the wait states for Flash, SRAM, and ROM based on the Clk_HF0 frequency and the current power mode. SRAM and ROM have two domains for the wait states – fast clock domain (Clk_Fast) and slow clock domain (Clk_Slow);...
Page 34 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture CPU subsystem (CPUSS) Table 4-3. Cortex®-M4 and Cortex®-M0+ Registers (continued) Name Type Reset value Description Undefined The program status register (PSR) combines: Application Program Status Register (APSR). Execution Program Status Register (EPSR). Interrupt Program Status Register (IPSR).
Page 35 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture CPU subsystem (CPUSS) Table 4-4. Cortex®-M4 PSR bit assignments (continued) Name Usage Register APSR Carry or borrow flag APSR Overflow flag APSR DSP overflow and saturation flag 26 – 25 EPSR IC/IT Control interrupt-continuable and IT instructions EPSR...
Page 36 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture CPU subsystem (CPUSS) Table 4-5. Cortex®-M0+ PSR bit assignments (continued) Name Usage Register 23 – 6 – – Reserved 5 – 0 IPSR Excepti Exception number of current ISR: 0 = thread mode Number 1 = reserved 2 = NMI...
Page 37 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture CPU subsystem (CPUSS) Instruction set Both CPUs implement subsets of the Thumb instruction set, as Table 4-6 shows. The table does not show the large number of variants and conditions of the instructions. For details, see one of the Arm® Cortex® generic user guides or technical reference manuals.
Page 38 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture SRAM controller SRAM controller This PSoC™ 6 MCU reference manual provides comprehensive and detailed information about the functions of the PSoC™ 6 MCU device hardware. It is divided into two books: architecture reference manual and registers reference manual.
Page 39 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture SRAM controller Partial AHB-Lite write transfers A partial AHB-Lite write transfer is translated into an SRAM read access and an SRAM write access. The SRAM read access is the direct result of the partial write transfer and the SRAM write access is the result of a write buffer request.
Page 40 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture SRAM controller Wait states The programmable wait states represent the number of clk_hf cycles for a read path through the SRAM memory to flipflops in either the fast domain (CM4 CPU) or slow domain (such as CM0+ CPU, DataWire, and DMA controller).
Page 41 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Inter-processor communication Inter-processor communication This PSoC™ 6 MCU reference manual provides comprehensive and detailed information about the functions of the PSoC™ 6 MCU device hardware. It is divided into two books: architecture reference manual and registers reference manual.
Page 42 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Inter-processor communication Architecture 6.2.1 IPC channel An IPC channel is implemented as five hardware registers, as shown in Figure 6-2. The IPC channel registers are accessible to all the processors in the system. •...
Page 43 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Inter-processor communication 6.2.2 IPC interrupt Each IPC interrupt line in the system has a corresponding IPC interrupt structure. An IPC interrupt can be triggered by a notify or a release event from any of the IPC channels in the system. You can choose to mask any of the sources of these events using the IPC interrupt registers.
Page 44 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Inter-processor communication IPC 0 IPC 1 IPC N Release Notify Release Notify Release Notify INTR N INTR N INTR N INTR N INTR N INTR N INTR 3 INTR 3 INTR 3 INTR 3 INTR 3 INTR 3...
Page 45 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Inter-processor communication Message passing IPC channels can be used to communicate messages between processors. In this use case, the channel is used in conjunction with the interrupt structures. The IPC channel is used to lock the access to the data register. The IPC channel is acquired by the sender and used to populate the message.
Page 46 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Inter-processor communication In the previous example, the size of the data being transmitted was just 32 bits. Larger messages can be sent as pointers. The sender can allocate a larger message structure in memory and pass the pointer in the 32-bit data register.
Page 47 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Inter-processor communication IPC Interrupt X System Interrupt IPC Channel X Core 0 Core 1 IPC Channel Y System IPC Interrupt Y Interrupt Data transfer/register updates over system bus Digital signals such as triggers or interrupts Figure 6-7.
Page 48 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Inter-processor communication 6.5.3 Half duplex with shared event handling In this model both the IPC channel and interrupt are shared between the two cores. Since the interrupt is also shared, the access to the interrupt registers must be managed using the IPC lock of the channel. As shown in Figure 6-9, the IPC interrupt will be set up to trigger interrupts in both cores.
Page 49 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Fault monitoring Fault monitoring This PSoC™ 6 MCU reference manual provides comprehensive and detailed information about the functions of the PSoC™ 6 MCU device hardware. It is divided into two books: architecture reference manual and registers reference manual.
Page 50 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Fault monitoring The PSoC™ 6 MCU family uses centralized fault report structures. This centralized nature allows for a system wide handling of faults simplifying firmware development. Only a single fault interrupt handler is required to monitor multiple faults.
Page 51 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Fault monitoring Table 7-1. Fault information Fault source Fault information MPU/SMPU violation DATA0[31:0]: Violating address. DATA1[0]: User read. DATA1[1]: User write. DATA1[2]: User execute. DATA1[3]: Privileged read. DATA1[4]: Privileged write. DATA1[5]: Privileged execute. DATA1[6]: Non-secure.
Page 52 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Fault monitoring 7.2.2 Signaling interface In addition to captured fault information, each fault report structure supports a signaling interface to notify the system about the captured fault. The interface of fault report structure ‘x’ supports the following: •...
Page 53 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Fault monitoring • One fault report structure is used to capture recoverable faults and one fault report structure is used to capture non-recoverable faults. The former can be used to generate a fault interrupt and the latter can be used to activate a chip output signal and/or activate a reset request.
Page 54 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Fault monitoring c) Use the signal externally for processing the fault – generate external reset, power cycle, or log fault information. 5. Set the RESET_REQ_EN bit [2] of the FAULT_STRUCTx_CTL register, if a soft reset is required on any fault detection in the structure.
Page 55 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Fault monitoring Table 7-2. Fault sources (continued) Fault index Source Description peri.group_vio[3] Peripheral group #3 (IOSS, UDB, LPCOMP, CSD, TCPWM, LCD, Bluetooth® LE) PPU violation Register address range: 0x40300000 to 0x403FFFFF peri.group_vio[4] Peripheral group #4 (SMIF) PPU violation Register address range: 0x40400000 to 0x404FFFFF...
Page 56 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Fault monitoring Table 7-3. Register list (continued) Name Description FAULT_STRUCTx_MASK0 Fault mask register 0 that enables the capture of pending faults with fault index from 0 to 31 by the fault structure FAULT_STRUCTx_MASK1 Fault mask register 1 that enables the capture of pending faults with fault index from 32 to 63 by the fault structure...
Page 57 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Interrupts Interrupts This PSoC™ 6 MCU reference manual provides comprehensive and detailed information about the functions of the PSoC™ 6 MCU device hardware. It is divided into two books: architecture reference manual and registers reference manual.
Page 58 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Interrupts Architecture PSoC™ 6 Interrupt Architecture M0+ interrupt settings Select Interrupt Source Enable / Disable Interrupt Set Priority Mask Interrupt M0+ Interrupt Set NMI source multiplexers Software trigger 240:1 IRQn can be connected to any one of the 147 32x8 (max 240) interrupt...
Page 59 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Interrupts Interrupts and exceptions - operation 8.3.1 Interrupt/exception handling The following sequence of events occurs when an interrupt or exception event is triggered: 1. Assuming that all the interrupt and exception signals are initially low (idle or inactive state) and the processor is executing the main code, a rising edge on any one of the signals is registered by the NVIC, if the interrupt or exception is enabled to be serviced by the CPU.
Page 60 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Interrupts 8.3.2 Level and pulse interrupts Both CM0+ and CM4 NVICs support level and pulse signals on the interrupt lines (IRQn). The classification of an interrupt as level or pulse is based on the interrupt source. IRQn IRQn is still high Execution...
Page 61 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Interrupts Table 8-1. M0+ exception vector table (continued) Exception Exception Exception priority Vector address number 12-13 Reserved Start_Address + 0x30 to Start_Address + 0x34 PendSupervisory (PendSV) Configurable (0 – 3) Start_Address + 0x38 System Timer (SysTick) Configurable (0 –...
Page 62 Cortex®-M0+ out of supervisory read-only memory (SROM). The boot code and other data in SROM memory are programmed by Infineon, and are not read/write accessible to external users. After completing the SROM boot sequence, the Cortex®-M0+ code execution jumps to flash memory.
Page 63 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Interrupts CPUSS_CM4_NMI_CTLx CPUSS_CM0P_NMI_CTLx INT Source 0 1023 System interrupt INT Source 1 sources CM4 NMI 1023 INT Source 2 n <= 1023 CM0+ NMI (device dependent) 1023 INT Source n-1 1023 Figure 8-5.
Page 64 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Interrupts 8.4.5 Bus Fault exception A Bus Fault is an exception that occurs because of a memory-related fault for an instruction or data memory transaction. This might be from an error detected on a bus in the memory system. The bus fault is supported only by the M4 core.
Page 65 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Interrupts 8.4.9 System Tick (SysTick) exception Both CM0+ and CM4 cores in PSoC™ 6 MCUs support a system timer, referred to as SysTick, as part of their internal architecture. SysTick provides a simple, 24-bit decrementing counter for various timekeeping purposes such as an RTOS tick timer, high-speed alarm timer, or simple counter.
Page 66 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Interrupts Table 8-3. List of PSoC™ 6 MCU interrupt sources (continued) System Cortex® M4 Power mode Interrupt source interrupt exception number IRQ11 Deep Sleep GPIO Interrupt - Port 11 IRQ12 Deep Sleep GPIO Interrupt - Port 12 IRQ13 Deep Sleep...
Page 67 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Interrupts Table 8-3. List of PSoC™ 6 MCU interrupt sources (continued) System Cortex® M4 Power mode Interrupt source interrupt exception number IRQ48 Active Serial Communication Block #7 IRQ49 Active CAPSENSE™ interrupt IRQ50 Active CPUSS DataWire #0, Channel #0...
Page 68 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Interrupts Table 8-3. List of PSoC™ 6 MCU interrupt sources (continued) System Cortex® M4 Power mode Interrupt source interrupt exception number IRQ85 Active Flash Macro Interrupt IRQ86 Active Cortex®-M0+ CTI #0 IRQ87 Active Cortex®-M0+ CTI #1...
Page 69 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Interrupts Table 8-3. List of PSoC™ 6 MCU interrupt sources (continued) System Cortex® M4 Power mode Interrupt source interrupt exception number IRQ122 Active UDB Interrupt #0 IRQ123 Active UDB Interrupt #1 IRQ124 Active UDB Interrupt #2...
Page 70 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Interrupts Interrupt/exception priority Exception priority is useful for exception arbitration when there are multiple exceptions that need to be serviced by the CPU. Both M4 and M0+ cores in PSoC™ 6 MCUs provide flexibility in choosing priority values for different exceptions.
Page 71 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Interrupts Figure 8-6. Interrupt Enable/Disable Registers Register Operation Bit value Comment Interrupt Set Enable Write To enable the interrupt Register No effect Read Interrupt is enabled Interrupt is disabled Interrupt Clear Enable Write To disable the interrupt Register...
Page 72 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Interrupts 8.8.1 Pending interrupts/exceptions When a peripheral generates an interrupt request signal to the NVIC or an exception event occurs, the corresponding exception enters the pending state. When the CPU starts executing the corresponding exception handler routine, the exception is changed from the pending state to the active state.
Page 73 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Interrupts 8.10 Interrupts and low-power modes The PSoC™ 6 MCU family allows device (CPU) wakeup from low-power modes when certain peripheral interrupt requests are generated. The Wakeup Interrupt Controller (WIC) block generates a wakeup signal that causes the CPU to enter Active mode when one or more wakeup sources generate an interrupt signal.
Page 74 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Interrupts d) Enable the exception, as explained in “Enabling and disabling interrupts” on page 70. 8.12 Register list Table 8-8. Register list Register name Description CPUSS_CM0_NMI_CTL Cortex®-M0+ NMI control register CPUSS_CM0_INT_CTL0 Cortex®-M0+ interrupt control 0 register CPUSS_CM0_INT_CTL1 Cortex®-M0+ interrupt control 1 register...
Page 75 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Protection units Protection units This PSoC™ 6 MCU reference manual provides comprehensive and detailed information about the functions of the PSoC™ 6 MCU device hardware. It is divided into two books: architecture reference manual and registers reference manual.
Page 76 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Protection units • Protection structure: A protection structure is a register structure in memory that sets up the rules based on which each protection unit will evaluate a transfer. Each protection unit associates itself to multiple protection structures.
Page 77 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Protection units – An MPU that is implemented as part of the bus infrastructure. This type is found in bus masters such as crypto and test controller. The definition of this MPU type follows the Arm® MPU definition (in terms of memory region and access attribute definition) to ensure a consistent software interface.
Page 78 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Protection units A protection violation results in a bus error and the bus transfer will not reach its target. An MPU or SMPU violation that targets a peripheral will not reach the associated protection evaluation (PPU). In other words, MPU and SMPU have a higher priority over PPU.
Page 79 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Protection units Register architecture The protection architecture has different conceptual pieces and different sets of registers correspond to each of these concepts. 9.3.1 Protection structure and attributes The MPU, SMPU, and PPU protection structure definition follows the Arm® definition. Each protection structure is defined by: •...
Page 80 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Protection units The execute and read access control attributes are orthogonal. Execute transfers are typically read transfers. To allow execute and read transfers in user mode, both ATT.UR and ATT.UX must be set to ‘1’. To allow data and read transfers in user mode, only ATT.UR must be set to ‘1’.
Page 81 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Protection units Note: • If no protection structure provides a match, the access is allowed. • If multiple protection structures provide a match, the access control attributes for the access evaluation are provided by the protection structure with the highest index.
Page 82 The Infineon code for the secure CPU, either in ROM or in flash, is considered trustworthy. The Infineon ROM code can be considered as the root of trust, and is used to authenticate Infineon flash code. Infineon code can be used to provide flash programming, secure provisioning, or other Infineon proprietary functionality.
Page 83 Hardware changes the protection context to 0 and Infineon-trusted software is responsible for re-establishing the protection context that applied before the Infineon-trusted code is entered. To this end, the secure CPU has two protection context fields in its MS_CTL register (hardware changes both fields): –...
Page 84 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Protection units Protection structures are 32 B aligned Two MMIO registers per protection structure MPU protection ADDR structures MPU protection structure 0 fault_req MPU protection fault_ack structure 1 fault_data Memory protection unit MPU protection (MPU) No protection...
Page 85 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Protection units 9.7.4 • The PPUs are situated in the PERI block and are associated with a peripheral group (a group of peripherals with a shared AHB-Lite bus infrastructure). A PPU is shared by all bus masters. The PPU distinguishes between different protection contexts;...
Page 86 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Protection units • Fixed protection structure pairs protect specific peripheral subregions (one pair for each subregion). The master structure protects the MMIO registers of the pair. The slave structure protects the peripheral subregion.
Page 87 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Protection units • Fixed protection structure pairs. These are 64-byte master/slave protection structure pairs, consisting of two 32-byte protection structures. These structures are used by the PPUs. Both structures have a fixed, constant address region.
Page 88 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Protection units PPU, programmable protection structure pair Slave structure ADDR Master structure Constant ADDR[23:0], encompassing master and slave Constant protection structures SUBREGION_DISABLE SMPU, programmable protection structure pair Slave structure ADDR Master structure Constant ADDR[23:0], encompassing master and slave Constant protection structures...
Page 89 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Protection units Note: By default, both CPUs (CM0+ and CM4) are in protection context 0 when they come out of reset. In protection context 0, the master is able to access all memory regardless of its protection settings. The master’s protection context will need to be changed from protection context 0 to make any protection structure configuration effective.
Page 90 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture DMA controller DMA controller This PSoC™ 6 MCU reference manual provides comprehensive and detailed information about the functions of the PSoC™ 6 MCU device hardware. It is divided into two books: architecture reference manual and registers reference manual.
Page 91 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture DMA controller A data transfer is initiated by an input trigger. This trigger may originate from the source peripheral of the transfer, the destination peripheral of the transfer, CPU software, or from another peripheral. Triggers provide Active/Sleep functionality and are not available in Deep Sleep and Hibernate power modes.
Page 92 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture DMA controller • The Privileged Mode (CHi_CTL.P) attribute can be set to privileged or user. • The Non-secure (CHi_CTL.NS) attribute can be set to secure or non-secure. A descriptor associated with each channel describes the data transfer. The descriptor is stored in memory and CHi_CURR_PTR provides the descriptor address associated with channel “i”...
Page 93 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture DMA controller 10.4 Descriptors The data transfer between a source and destination in a channel is configured using a descriptor. Descriptors are stored in memory. The descriptor pointer is specified in the DMA channel registers. The DMA controller does not modify the descriptor and treats it as read only.
Page 94 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture DMA controller 1D transfer: The following pseudo code illustrates a 1D transfer. Note that the 1D transfer is represented by a loop with each iteration executing a single transfer. // DST_ADDR is a pointer to an object of type defined by DST_TRANSFER_SIZE // SRC_ADDR is a pointer to an object of type defined by SRC_TRANSFER_SIZE // t_DATA_SIZE is the type associated with the DATA_SIZE for (X_IDX = 0;...
Page 95 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture DMA controller 10.4.1 Address configuration Source and destination address: The source and destination addresses are set in the respective registers in the descriptor. These set the base addresses for the source and destination location for the transfer. In case the descriptor is configured to transfer a single element, this field holds the source/destination address of the data element.
Page 96 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture DMA controller • 0 – Pulse Trigger: Do not wait for deactivation. When a trigger is detected, the transfer is initiated. After completing the transfer, if the trigger is still active then it is considered as another trigger and the subsequent transfer is initiated immediately.
Page 97 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture DMA controller 10.4.2 Transfer size The word width for a transfer can be configured using the transfer/data size parameter in the descriptor. The settings are diversified into source transfer size, destination transfer size, and data size. The data size parameter (DATA_SIZE) sets the width of the bus for the transfer.
Page 98 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture DMA controller 10.5 DMA controller Pending Priority Data Transfer Engine Trigger out System triggers Decoder (active request) Triggers Interrupt Bus slave Bus master Trigger interface registers interface Multiplexer Descriptors Descriptors Descriptors Memory Figure 10-3.
Page 99 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture DMA controller 10.5.3 Output triggers Each channel has an output trigger. This trigger is high for two slow clock cycles. The trigger is generated on the completion of a data transfer. At the system level, these output triggers can be connected to the trigger multiplexer component.
Page 100 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture DMA controller Table 10-4. DMA steps and performance (continued) Operation Cycles Load descriptors 4 for single transfer 5 for 1-D transfer 6 for 2-D transfer Load next pointer Moving data from source to destination Total 14 for single transfer For subsequent transfers on a preloaded descriptor, cycles are needed only to move the data from source to...
Page 101 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture DMA controller • Bus arbitration: Several bus masters access the bus, including the CPU cores and multiple DMA (DW) and DMAC. This makes any access to data movement over the bus subject to arbitration with other masters. Actions such as fetching the descriptor or data can be stalled by arbitration.
Page 102 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Cryptographic function block (Crypto) Cryptographic function block (Crypto) This PSoC™ 6 MCU reference manual provides comprehensive and detailed information about the functions of the PSoC™ 6 MCU device hardware. It is divided into two books: architecture reference manual and registers reference manual.
Page 103 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Cryptographic function block (Crypto) The crypto block has the following interfaces: • An AHB-Lite slave interface connects the block to the AHB-Lite infrastructure. This interface supports 8/16/32- bit AHB-Lite transfers. MMIO register accesses are 32-bit only. Memory buffer accesses can be 8/16/32-bit. •...
Page 104 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Cryptographic function block (Crypto) SDRAM AHB-Lite master SDRAM controller FLASH SRAM (e.g. CPU) AHB-Lite infrastructure AHB-Lite sIave I/F AHB-Lite master I/F AHB-Lite slave interface AHB-Lite master interface Retention in DeepSleep Memory buffer (SRAM) power mode Memory interface rsrc0...
Page 105 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Cryptographic function block (Crypto) 11.4 Instruction controller The instruction controller consists of an instruction FIFO, an instruction decoder and a general-purpose register- file. • The instruction FIFO is SW programmable through MMIO registers that are accessed through the AHB-Lite slave interface.
Page 106 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Cryptographic function block (Crypto) • Generic instructions: SET_REG1, SET_REG2, SET_REG3, SET_REG4, SYNC The generic STE_REGx instructions write 32-bit data to registers-file registers. These instructions are the only registers that use a group of FIFO entries; all other instructions are contained within a single FIFO entry. The SET_REG1 instruction and operands uses two FIFO entries and writes a single register-file register, the SET_REG2 instruction and operands uses three FIFO entries and writes two register-file registers, and so on.
Page 107 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Cryptographic function block (Crypto) Table 11-4. SET_REG4 instruction Instruction format SET_REG4 (rdst0, data0, rdst1, data1, rdst2, data2, rdst3, data3) rdst0: register operand data0: 32 bit immediate data rdst1: register operand data1: 32 bit immediate data rdst2: register operand data2: 32 bit immediate data rdst3: register operand...
Page 108 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Cryptographic function block (Crypto) Table 11-5. SYNC instruction Instruction format SYNC (imm8[7:0]) imm12: 12-bit immediate date Encoding IW[31:24] = “operation code” = 0x7f IW[7:0] = imm8 Functionality The 8-bit immediate value bit fields specify what components must have their instructions completed: Bit 0: AES component.
Page 109 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Cryptographic function block (Crypto) – ERROR_STATUS1.DATA24[0] is set to ‘0’ for a write transfer and ‘1’ for a read transfer. ERROR_STATUS1.DATA24[5:4] is set to ‘0’ for a 8-bit transfer, ‘1’ for a 16-bit transfer, ‘2’ for a 32-bit transfer. ERROR_STATUS0.DATA32[] is set with the violating transfer address.
Page 110 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Cryptographic function block (Crypto) Table 11-6. DES_BLOCK instruction Instruction format DES_BLOCK (rsrc2, rsrc1, rsrc0) rsrc2: register operand rsrc1: register operand rsrc0: register operand Encoding IW[31:24] = “operation code” = 0x70 IW[11:8] = rsrc2 IW[7:4] = rsrc1 IW[3:0] = rsrc0 Functionality...
Page 111 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Cryptographic function block (Crypto) Table 11-9. TDES_BLOCK_INV instruction Instruction format TDES_BLOCK_INV (rsrc2, rsrc1, rsrc0) rsrc2: register operand rsrc1: register operand rsrc0: register operand Encoding IW[31:24] = “operation code” = 0x73 IW[11:8] = rsrc2 IW[7:4] = rsrc1 IW[3:0] = rsrc0 Functionality...
Page 112 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Cryptographic function block (Crypto) Table 11-11. AES_BLOCK instruction Instruction format AES_BLOCK (rsrc3, rsrc1, rsrc0) rsrc3: register operand rsrc1: register operand rsrc0: register operand Encoding IW[31:24] = “operation code” = 0x44 IW[15:12] = rsrc3 IW[7:4] = rsrc1 IW[3:0] = rsrc0 Functionality...
Page 113 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Cryptographic function block (Crypto) Table 11-14. AES_KEY_INV instruction Instruction format AES_KEY_INV (rsrc1, rsrc0) rsrc2: register operand rsrc0: register operand Encoding IW[31:24] = “operation code” = 0x47 IW[11:8] = rsrc2 IW[3:0] = rsrc0 Functionality Perform AES block cipher to generate the block cipher key from the inverse block cipher key.
Page 114 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Cryptographic function block (Crypto) Block cipher Inverse block cipher Memory interface rsrc0: ”key” rsrc1: “plaintext” rsrc0: “inverse key” rsrc1: “ciphertext” Plaintext data Ciphertext data p[127:0] c[127:0] Start key Start key irk [127:0] Forward Round 0 Inverse Round 0...
Page 115 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Cryptographic function block (Crypto) The SHA256 and SHA224 algorithms are the same. However, the initial hash value and the size of the message digest are different. SW provides the algorithm specific hash value “hash_init” and selects the message digest from the calculated hash value “hash”.
Page 116 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Cryptographic function block (Crypto) Figure 11-5 illustrates the SHA functionality. Memory interface rsrc0: “block start address” rsrc1: “initial hash value address” Initialize working registers with initial hash value Produce round constants Round 0 Round 1 Round 62...
Page 117 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Cryptographic function block (Crypto) Table 11-18. STR_MEMSET instruction Instruction format STR_MEMSET (rsrc2, rsrc1, rsrc0) rsrc2: register operand rsrc1: register operand rsrc0: register operand Encoding IW[31:24] = “operation code” = 0x51 IW[15:12] = rsrc2 IW[11:8] = rsrc1 IW[3:0] = rsrc0 Functionality...
Page 118 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Cryptographic function block (Crypto) Table 11-20. STR_MEMXOR instruction Instruction format STR_MEMXOR (rsrc3, rsrc2, rsrc1, rsrc0) Rsrc3: register operand rsrc2: register operand rsrc1: register operand rsrc0: register operand Encoding IW[31:24] = “operation code” = 0x53 IW[15:12] = rsrc3 IW[11:8] = rsrc2 IW[7:4] = rsrc1...
Page 119 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Cryptographic function block (Crypto) Table 11-21. CRC instruction Instruction format CRC (rsrc1, rsrc0) rsrc1: register operand rsrc0: register operand Encoding IW[31:24] = “operation code” = 0x58 IW[7:4] = rsrc1 IW[3:0] = rsrc0 Functionality Perform CRC function.
Page 120 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Cryptographic function block (Crypto) Different CRC algorithms require different seed values and have different requirements for XOR functionality and bit reversal. Table 11-22 provides the proper settings for the CRC32, CRC16-CCITT, and CRC16 algorithms. The table also provides the remainder after the algorithms are performed on a five-byte array {0x12, 0x34, 0x56, 0x78, 0x9a}.
Page 121 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Cryptographic function block (Crypto) The final pseudo random bit is the XOR of the three bits that are generated by the individual LFSRs. LFSR32 output LFSR31 output pseudo random unit LFSR29 output Figure 11-9.
Page 122 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Cryptographic function block (Crypto) In other words the correction step only produces a bit on a ‘0’ to ‘1’ or ‘1’ to ‘0’ transition. Note that for a random input bit sequence, the correction step produces an output bit sequence of roughly one-quarter the frequency of the input bit sequence (the input reduction bits are processed in non-overlapping pairs and only half of the pair encodings result in an output bit).
Page 123 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Cryptographic function block (Crypto) • RO15: A fixed ring oscillator consisting of 15 inverters. • GARO15: A fixed Galois-based ring oscillator of 15 inverters. • GARO31: A flexible Galois-based ring oscillator of up to 31 inverters. A programmable polynomial of up to order 31 provides the flexibility in the oscillator feedback.
Page 124 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Cryptographic function block (Crypto) output Figure 11-13. Flexible Galois-based ring oscillators: GARO31 When the ring oscillator is disabled (GARO31_EN is ‘0’), the polynomial is forced to “0” and the ring is broken as illustrated by Figure 11-14.
Page 125 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Cryptographic function block (Crypto) output Figure 11-16. Flexible Fibonacci-based ring oscillators: FIRO31 When the ring oscillator is disabled (FIRO31_EN is ‘0’), the polynomial is forced to “0” and the ring is broken as illustrated by Figure 11-17.
Page 126 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Cryptographic function block (Crypto) The TRNG has a built-in health monitor that performs tests on the digitized noise source to detect deviations from the intended behavior. For example, the health monitor detects “stuck at” faults in the digitized analog samples. The health monitor tests one out of three selected digitized bit streams: •...
Page 127 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Cryptographic function block (Crypto) Post-processing digitized INIT_DELAY[] RED_CLOCK_DIV[] analog samples (DAS) true random von Neumann corrector Health monitor DAS_SEL RED_SEL TR_SEL BITSTREAM_SEL[] Adaptive proportion START_RC Repetition count test START_AP test CUTOFF_COUNT[] CUTOFF_COUNT[] WINDOW_SIZE[] OCC_COUNT[]...
Page 128 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Cryptographic function block (Crypto) The VU uses the instruction controller register file. The VU uses the 32-bit registers as (data, size) pair: a 14-bit data field (bits 29 down to 16), and a 12-bit size field (bits 11 down to 0). The data field is either used as operand data or as a pointer into the memory buffer.
Page 129 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Cryptographic function block (Crypto) The example illustrates that the full expressive power of the C language is available when writing SW for the VU. The example also illustrates that relatively complex functionality can be expressed in only a few lines of C code (consider implementing the same functionality on a 32-bit Arm®...
Page 130 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Cryptographic function block (Crypto) 11.13.2 Stack The VU component stack resides in the memory buffer. Register r15 is used as a stack pointer. The stack has two purposes: • It is used to save/restore registers r0 through r14. Each register (data field and size field) uses a single 32-bit stack element.
Page 131 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Cryptographic function block (Crypto) Register-file Memory buffer size[11:0] data[13:0] size[11:0] data[13:0] size[11:0] data[13:0] r15/sp don’t care Figure 11-22. Register-file state after FREE_MEM instruction Freeing of stack elements should be in the reversed order of allocation of stack elements. See the description of the FREE_MEM instruction for the order in which registers are freed (lower registers are freed before higher registers).
Page 132 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Cryptographic function block (Crypto) Note that the instruction execution time (in clock cycles) is typically independent of the instruction operand data. The execution time is however dependent on the size of memory buffer operands (as specified by the register size field).
Page 133 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Cryptographic function block (Crypto) Operand types. Typically, VU instruction operands all have the same type: either register operands or memory buffer operands. However, some exceptions do exist. For example, consider the following CTSAME (count trailing same) instruction.
Page 134 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Cryptographic function block (Crypto) 11.13.7 Instruction set This section describes all VU instructions. For each instruction, the following is described: • The instruction format – Source operand types (register or memory operands) –...
Page 135 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Cryptographic function block (Crypto) Table 11-28. Instructions with register operand only, Category I Instruction format Mnemonic (rdst, imm14[13:0], imm12[11:0]) rdst: register operand imm14: 14-bit immediate (for register data field) imm12: 12-bit immediate (for register size field) Encoding IW[31:30] = “operation code”...
Page 136 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Cryptographic function block (Crypto) Table 11-31. ST_REG instruction Instruction format Mnemonic (rsrc1, rsrc0) or COND_Mnemonic (cc, rsrc1, rsrc0) rsrc1: register operand rsrc0: register operand cc: condition code Encoding IW[31:24] = “operation code” IW[23:20] = cc IW[7:4] = rsrc1 IW[3:0] = rsrc0...
Page 137 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Cryptographic function block (Crypto) Table 11-34. Instructions with register operand only, Category V Instruction format Mnemonic (rdst) or COND_Mnemonic (cc, rdst) rdst: register operand cc: condition code Encoding IW[31:24] = “operation code” IW[23:20] = cc IW[15:12] = rdst Mnemonic...
Page 138 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Cryptographic function block (Crypto) Table 11-36. Instructions with register operand only, Category VII Instruction Mnemonic (rdst, rsrc1, rsrc0) or COND_Mnemonic (cc, rdst, rsrc1, format rsrc0) rdst: register operand rsrc1: register operand rsrc0: register operand cc: condition code Encoding...
Page 139 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Cryptographic function block (Crypto) Table 11-37. Instructions with mixed operands, Category I Instruction format Mnemonic (rdst, rsrc1, rsrc0) or COND_Mnemonic (cc, rdst, rsrc1, rsrc0) rdst: memory buffer operand rsrc1: memory buffer operand rsrc0: register operand cc: condition code Encoding...
Page 140 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Cryptographic function block (Crypto) Table 11-38. Instructions with mixed operands, Category II Instruction format Mnemonic (rdst, rsrc) or COND_Mnemonic (cc, rdst, rsrc) rdst: memory buffer operand rsrc: memory buffer operand cc: condition code Encoding IW[31:24] = “operation code”...
Page 141 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Cryptographic function block (Crypto) Table 11-39. Instructions with mixed operands, Category III Instruction format Mnemonic (rdst, rsrc) or COND_Mnemonic (cc, rdst, rsrc) rdst: memory buffer operand rsrc: register operand cc: condition code Encoding IW[31:24] = “operation code”...
Page 142 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Cryptographic function block (Crypto) Table 11-41. Instructions with mixed operands, Category V Instruction format Mnemonic (rdst, rsrc1, rsrc0) or COND_Mnemonic (cc, rdst, rsrc1, rsrc0) rdst: register operand rsrc1: memory buffer operand rsrc0: memory buffer operand cc: condition code Encoding...
Page 143 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Cryptographic function block (Crypto) Table 11-42. Instructions with memory buffer operands, Category I Instruction format Mnemonic (rdst) or COND_Mnemonic (cc, rdst) rdst: memory buffer operand cc: condition code Encoding IW[31:24] = “operation code” IW[23:20] = cc IW[15:12] = rdst Shared functionality...
Page 144 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Cryptographic function block (Crypto) Table 11-43. Instructions with memory buffer operands, Category II Instruction format Mnemonic (rdst, rsrc) or COND_Mnemonic (cc, rdst, rsrc) rdst: memory buffer operand rsrc: memory buffer operand cc: condition code Encoding IW[31:24] = “operation code”...
Page 145 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Cryptographic function block (Crypto) Table 11-44. Instructions with memory buffer operands, Category III Instruction format Mnemonic (rsrc1, rsrc0) or COND_Mnemonic (cc, rsrc1, rsrc0) rsrc1: memory buffer operand rsrc0: memory buffer operand cc: condition code Encoding IW[31:24] = “operation code”...
Page 146 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Cryptographic function block (Crypto) Table 11-46. Instructions with memory buffer operands, Category V Instruction format Mnemonic (rdst, rsrc1, rsrc0) or COND_Mnemonic (cc, rdst, rsrc1, rsrc0) rdst: memory buffer operand rsrc1: memory buffer operand rsrc0: memory buffer operand cc: condition code Encoding...
Page 147 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Cryptographic function block (Crypto) Table 11-46. Instructions with memory buffer operands, Category V (continued) Instruction format Mnemonic (rdst, rsrc1, rsrc0) or COND_Mnemonic (cc, rdst, rsrc1, rsrc0) rdst: memory buffer operand rsrc1: memory buffer operand rsrc0: memory buffer operand cc: condition code 0x36...
Page 148 The PSoC™ 6 MCU Program and Debug interface provides a communication gateway for an external device to perform programming or debugging. The external device can be a Infineon-supplied programmer and debugger, or a third-party device that supports programming and debugging. The serial wire debug (SWD) or the JTAG interface can be used as the communication protocol between the external device and PSoC™...
Page 149 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Program and debug interface PSoC™ 6 MCU Arm® Cortex®-M0+ subsystem CM0+ AHB decoder CM0 Access Port Cross Trigger CM0 external Cortex®-M0+ Interface (CTI) ROM table Micro Trace Buffer (MTB) SRAM Arm® Cortex®-M4 subsystem CM4 APB decoder CM4 AP Cross Trigger...
Page 150 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Program and debug interface 12.2.1 Debug access port (DAP) The DAP consists of a combined SWD/JTAG interface (SWJ) that also includes the SWD listener. The SWD listener decides whether the JTAG interface (default) or SWD interface is active. Note that JTAG and SWD are mutually exclusive because they share pins.
Page 151 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Program and debug interface 12.2.2 ROM tables The ROM tables are organized in a tree hierarchy. Each AP has a register that contains a 32-bit address pointer to the base of the root ROM table for that AP. For PSoC™ 6 MCUs, there are three such root ROM tables. Each ROM table contains 32-bit entries with an address pointer that either points to the base of the next level ROM table.
Page 152 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Program and debug interface 12.3 Serial wire debug (SWD) interface The PSoC™ 6 MCU supports programming and debugging through the SWD interface. The SWD protocol is a packet-based serial transaction protocol. At the pin level, it uses a single bidirectional data signal (SWDIO) and a unidirectional clock signal (SWDCK).
Page 153 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Program and debug interface g) The park bit is always logic 1. 2. Target acknowledge response phase: SWDIO driven by the target a) The ACK[2:0] bits represent the target to host response, indicating failure or success, among other results. Table 12-1 for definitions.
Page 154 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Program and debug interface 12.3.2 ACK details The acknowledge (ACK) bitfield is used to communicate the status of the previous transfer. OK ACK means that previous packet was successful. A WAIT response requires a data phase. For a FAULT status, the programming operation should be aborted immediately.
Page 155 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Program and debug interface Device 1 Device 2 Device 3 Figure 12-3. JTAG interface to multiple ICs on a circuit board The JTAG interface architecture within each device is shown in Figure 12-4.
Page 156 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Program and debug interface TMS = 1 test logic reset TMS = 0 TMS = 0 run test idle TMS = 1 TMS = 1 TMS = 1 select dr scan select ir scan TMS = 0 TMS = 0...
Page 157 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Program and debug interface 12.5 Programming the PSoC™ 6 MCU The PSoC™ 6 MCU is programmed using the following sequence. See the PSoC™ 6 MCU programming specifications for complete details on the programming algorithm, timing specifications, and hardware configuration required for programming.
Page 158 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Program and debug interface 12.6 Registers Table 12-3. List of registers Register name Description CM0P_DWT Cortex® M0+ Data Watchpoint and Trace (DWT) registers CM0P_BP Cortex® M0+ BreakPoint (BP) registers CM0P_ROM Cortex® M0+ CPU Coresight ROM table CM0P_CTI Cortex®...
Page 159 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Nonvolatile memory Nonvolatile memory This PSoC™ 6 MCU reference manual provides comprehensive and detailed information about the functions of the PSoC™ 6 MCU device hardware. It is divided into two books: architecture reference manual and registers reference manual.
Page 160 The SFlash region is used to store trim parameters, system configuration parameters, protection and security settings, boot code, and other Infineon proprietary information. Read access to this region is permitted, but program/erase access is limited. The application region is used to store code images or data. The AUXFlash is typically used for EEPROM emulation.
Page 161 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Nonvolatile memory 13.1.4 Flash controller Access to the flash memory is enabled through the flash controller. The flash controller interfaces with the AHB- Lite bus and provides flash access for the CM0+, CM4, Crypto, DataWire, and debug. The flash controller generates a bus error if: •...
Page 162 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Nonvolatile memory 13.1.4.3 CPU caches The flash controller provides 8 kB caches for both the CM0+ and CM4 CPUs. Each cache is a four-way set associative with a least recently used (LRU) replacement scheme. Four-way set associativity means that each cache has four ways per set, with each way containing a valid bit, tag, and data.
Page 163 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Nonvolatile memory 13.2 Flash memory programming 13.2.1 Features • SROM API library for flash management through system calls such as Program Row, Erase Flash, and Blow eFuse • System calls can be performed using CM0+, CM4, or DAP 13.2.2 Architecture Flash programming operations are implemented as system calls.
Page 164 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Nonvolatile memory CM4 or CM0+ A pointer is always used to structure SRAM. Commands that are issued as a single word by DAP can still be issued by CM0+ or CM4, but use an SRAM structure instead. The NMI interrupt handler for system calls works as follows.
Page 165 APIs. Table 13-5. List of system calls System call Opcode Description Access allowed category Normal Secure Dead “Infineon ID” 0x00 Returns die ID, CM0+, CM4, CM0+, CM4, CM0+, CM4, page 166 major/minor ID, and protection state “Blow eFuse bit”...
Page 166 ID type based on which it will return family ID and revision ID if the ID type is set to ‘0’, and silicon ID and protection state if the ID type is set to ‘1’. Table 13-6. Infineon ID Infineon IDs...
Page 167 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Nonvolatile memory Parameters if DAP is master Address Value to be written Description IPC_STRUCT_DATA Register Bits [31:24] 0x00 Silicon ID opcode. Bits [15:8] 0 - returns 0. Read family ID and revision ID ID type.
Page 168 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Nonvolatile memory Return if DAP Invoked the system call Address Return value Description IPC_STRUCT_DATA Register Bits [7:0] If ID type = 0, Family ID Lo See the device datasheet for silicon ID values for If ID type = 1, Silicon ID Lo different part numbers.
Page 169 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Nonvolatile memory Return if CM0+/CM4 invoked the system call Address Return value Description SRAM_SCRATCH Register Bits [7:0] If ID type = 0, Family ID Lo See the device datasheet for silicon ID values for If ID type = 1, Silicon ID Lo different part numbers.
Page 170 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Nonvolatile memory 13.5.2 Blow eFuse bit This function blows the addressed eFuse bit. The read value of a blown eFuse bit is ‘1’ and that of an unblown eFuse bit is ‘0’. These values are returned to the IPC_STRUCT_DATA register. Parameters are passed through the IPC_STRUCT_DATA register.
Page 171 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Nonvolatile memory 13.5.3 Read eFuse byte This function returns the eFuse contents of the addressed byte. The read value of a blown eFuse bit is ‘1’ and that of an unblown eFuse bit is ‘0’. These values are returned to the IPC_STRUCT_DATA register. Parameters are passed through the IPC_STRUCT_DATA register.
Page 172 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Nonvolatile memory 13.5.4 Write row This function is used to program the flash. You must provide data to be loaded and the flash address to be programmed. The WriteRow parameter performs pre-program and erase, and then programs the flash row with contents from the row latch.
Page 173 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Nonvolatile memory Parameters if DAP/CM0+/CM4 is master Address Value to be written Description IPC_STRUCT_DATA Register Bits [31:0] SRAM_SCRATCH_ADDR SRAM address where the API parameters are stored. This must be a 32-bit aligned address. SRAM_SCRATCH Register Bits [31:24] 0x05...
Page 174 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Nonvolatile memory Return if DAP/CM0+/CM4 invoked the system call Address Return value Description SRAM_SCRATCH Register Bits [27:0] Error code (if any) “System call status” on page 191 for details. Bits [31:28] 0xA = SUCCESS/Program Status code (see “System call status”...
Page 175 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Nonvolatile memory Parameters if DAP/CM0+/CM4 is master Address Value to be written Description IPC_STRUCT_DATA Register Bits [31:0] SRAM_SCRATCH_ADDR SRAM address where the API parameters are stored. This must be a 32-bit aligned address. SRAM_SCRATCH Register Bits[31:24] 0x06...
Page 176 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Nonvolatile memory Return if DAP/CM0+/CM4 invoked the system call Address Return value Description SRAM_SCRATCH Register Bits [27:0] Error code (if any) “System call status” on page 191 for details. Bits [31:28] 0xA = SUCCESS/Program Status code (see “System call status”...
Page 177 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Nonvolatile memory Parameters if CM0+/CM4 is master Address Value to be written Description IPC_STRUCT_DATA Register Bits [31:0] SRAM_SCRATCH_ADDR SRAM address where the API parameters are stored. This must be a 32-bit aligned address. SRAM_SCRATCH Register Bits [31:24] 0x0A...
Page 178 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Nonvolatile memory 13.5.7 Checksum This function reads either the entire flash or a row of flash, and returns the sum of each byte read. Bytes 1 and 2 of the parameters select whether the checksum is performed on the entire flash or on a row of flash. This function will inherit the identity of the master that called the function.
Page 179 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Nonvolatile memory Return if CM0+/CM4 invoked the system call Address Return value Description SRAM_SCRATCH Register Bits [23:0] Checksum Checksum if status is SUCCESS Bits [27:24] 0xXX Not used (don’t care) Bits [31:28] 0xA = SUCCESS Status code (see “System call status”...
Page 180 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Nonvolatile memory 13.5.9 ConfigureRegionBulk This API writes a 32-bit data value to a set of contiguous addresses. It cannot be used to configure protected registers or flash. The Start and End addresses of the region are configurable but must be within a writable area. The region must also be 32-bit aligned.
Page 181 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Nonvolatile memory 13.5.10 DirectExecute This function directly executes code located at a configurable address. This function is only available in normal life-cycle state if the DIRECT_EXECUTE_DISABLE bit is 0. Parameters if DAP is master Address Value to be written Description...
Page 182 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Nonvolatile memory Parameters if DAP/CM0+/CM4 is master Address Value to be written Description IPC_STRUCT_DATA Register Bits [31:0] SRAM_SCRATCH_ADDR SRAM address where the API parameters are stored. This must be a 32-bit aligned address. SRAM_SCRATCH Register Bits [31:24] 0x14...
Page 183 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Nonvolatile memory 13.5.12 Soft reset This function resets the system by setting CM0+ AIRCR system reset bit. This will result in a system-wide reset, except debug logic. This API can also be used for selective reset of only the CM4 core based on the ‘Type’ parameter.
Page 184 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Nonvolatile memory 13.5.13 Erase row This function erases the specified row. You must provide the address of the row that needs to be erased. The values are returned to the IPC_STRUCT_DATA register. Parameters are passed through the IPC_STRUCT_DATA register.
Page 185 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Nonvolatile memory Return if DAP/CM0+/CM4 invoked the system call Address Return value Description SRAM_SCRATCH Register Bits [27:0] Error code (if any) “System call status” on page 191 for details. Bits [31:28] 0xA = SUCCESS Status code (see “System call status”...
Page 186 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Nonvolatile memory Return if DAP/CM0+/CM4 invoked the system call Address Return value Description SRAM_SCRATCH Register Bits [23:0] Error code (if any) “System call status” on page 191 for details. Bits [31:28] 0xA = SUCCESS Status code (see “System call status”...
Page 187 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Nonvolatile memory 13.5.16 ReadUniqueID This function returns the unique ID of the die from SFlash. Parameters if DAP/ CM0+/CM4 is master Address Value to be written Description IPC_STRUCT_DATA Register Bits[31:0] SRAM_SCRATCH_ADDR SRAM address where the API parameters are stored.
Page 188 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Nonvolatile memory 13.5.17 CheckFactoryHash This function generates the FACTORY_HASH according to the TOC1 and compares the value with the FACTORY1_HASH eFuse value. Parameters if DAP is master Address Value to be written Description IPC_STRUCT_DATA Register Bits [31:24]...
Page 189 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Nonvolatile memory 13.5.18 TransitionToRMA This function converts the part from SECURE, SECURE_WITH_DEBUG, or NORMAL to the RMA life-cycle stage. This API performs eFuse programming, VDD should be set to 2.5 V for successful programming. This function uses Flash Boot functions.
Page 190 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Nonvolatile memory 13.5.19 ReadFuseByteMargin This API returns the eFuse contents of the addressed byte read marginally. The read value of a blown bit is ‘1’ and of a not blown bit is ‘0’. Parameters if DAP is master Address Value to be written...
Page 191 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Nonvolatile memory Return if CM0+/CM4 invoked the system call Address Return value Description SRAM_SCRATCH Register Bits [31:28] 0xA = SUCCESS Status code (see “System call status” on page 191 0xF = ERROR for details).
Page 192 TOC1. The FACTORY_HASH is stored in eFuse before the device leaves Infineon. The data integrity of selected objects in both TOC1 and TOC2 must be verified as part of authentication of Flash boot by ROM boot in the SECURE life-cycle stage.
Page 193 0x04 Magic number (0x01211219) protection state 0x08 Number of objects starting from offset 0xC to be verified for by Infineon FACTORY_HASH 0x0C Address of Trims stored in SFlash 0x10 Address of Unique ID (fixed size of 12 bytes) stored in SFlash...
Page 194 Address of First User Application Object 0x14 0x16007C14 TOC2_FIRST_USER_APP_F First Application Object Format (4 bytes). 0 means ORMAT Basic Application Format, 1 means Infineon Secure Application Format, and 2 means Simplified Secure Application Format 0x18 0x16007C18 TOC2_SECOND_USER_APP Address of Second User Application Object (0's if...
Page 195 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Boot code Table 14-3. TOC2_FLAGS bits, default settings, and descriptions TOC2_FLAGS Name Default Description bits CLOCK_CONFIG Indicates the CM0+ CPU clock frequency configuration. The clock will remain at this setting after flash boot execution.
Page 196 This life-cycle stage allows Failure Analysis (FA). The part is transitioned to the RMA life-cycle stage when the customer wants Infineon to perform failure analysis. The customer erases all sensitive data before invoking the system call that transitions the part to RMA.
Page 197 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Boot code Table 14-7. DAP Access Restriction Registers for normal, secure, and dead protection states (all default to 0) Bits Name Description CM0_AP_DISABLE A ‘1’ indicates that this device does not allow access to the M0+ debug access port.
Page 198 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Boot code Table 14-8. SECURE_ACCESS_RESTRICT1, DEAD_ACCESS_RESTRICT1, and NORMAL_ACCESS_RESTRICTIONS [15:8] Registers (All default to 0) Bits Name Description FLASH_ALLOWED This field indicates what portion of the main flash is accessible through the system debug access port. Only the portion starting at the bottom of flash (0x1000_0000) is exposed to the system DAP.
Page 199 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Boot code As shown in Figure 14-2, if you want to limit the lower fourth of flash of a device with 2MB of flash, write a ‘4’ into the FLASH_ALLOWED field. Only the flash area between 0x10000000 and 0x1007FFFF will be accessible via the SYS_DAP.
Page 200 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Boot code Table 14-10. Protection structures set up during boot process (continued) Protection structure Protection Attribute Protected region Region Region (Read/Write) settings base size (Bytes) PERI_MS_PPU_PROG_STRUC Write only in ATT0: AP_CTL, 0x40210500 24 0x87FFFE49 CPUSS_PROTECTI...
Page 201 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Boot code RESET Get M4 Reset Vector I am M0+? CM4_VECTOR_TABLE_BASE (CPUSS MMIO) (CPUSS MMIO) Set RST SP Goto RST PC Get M0+ Reset Vector PROTECTION==UNKOWN ? CM0_VECTOR_TABLE_BASE (CPUSS MMIO) (CPUSS MMIO) Set RST SP (Warm Boot Goto RST PC...
Page 202 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Boot code 14.3 Flash boot 14.3.1 Overview The second stage of boot, Flash boot, is entered after ROM boot has authenticated the Flash boot image if the device is in the SECURE or SECURE_WITH_DEBUG life-cycle stage, or if the APP_AUTH_DISABLE field is not set in TOC2.
Page 203 The Flash boot application version • The number of cores (set to ‘1’ for Flash boot) • CM0+ vector table offset • Infineon ID and CPU Core Index 14.3.4.2 Code segment The CM0 code segment consists of: • CM0+ vector table •...
Page 204 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Boot code 14.3.5 Flash boot flow chart The Flash boot program flow is shown in Figure 14-5. The entry point is a fixed offset in SFlash. Each section of the flow chart is labeled with an index number. In the sections following the flow chart, explanations of each step are provided with the associated index number.
Page 205 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Boot code 14.3.5.1 Entry from ROM boot (0) ROM boot transfers control to Flash boot after it validates the SFlash block and TOC1 in the user flash. 14.3.5.2 Basic initialization (1) This stage sets the value of the stack pointer during runtime.
Page 206 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Boot code 14.3.5.7 Is reset handler valid? (6) Flash boot checks if the address of the reset handler for the user application is in RAM, SFlash, application flash, or AUXFlash. 14.3.5.8 Authenticate app? (7) Flash boot optionally authenticates a digital signature for the application image if the TOC2_FLAGS bit APP_AUTH_DISABLE = 1.
Page 207 Application Format” and the application start address is the start of the user flash. If the TOC2 is valid and the life-cycle stage is NORMAL, then the application can be in either the Basic or Infineon Standard Secure application formats.
Page 208 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Boot code 14.3.5.18 Set up SP (17) The SP register value for Flash boot is at the top of user RAM. 14.3.5.19 Idle loop (18) Before going to an idle loop the Flash boot sets the CPUSS_CM0_VECTOR_TABLE_BASE MMIO register to 0xFFFF_0000.
Page 209 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Boot code Table 14-11. Error code (continued) Error name Value Description CY_FB_ERROR_BOOT_LIN_INIT 0xF100_0141 Bootloader error, LIN initialization failed CY_FB_ERROR_BOOT_LIN_SET_CMD 0xF100_0142 Bootloader error, LinSetCmd() failed 14.3.5.21 Protection = Virgin? (31) The CPUSS_PROTECTION MMIO register value is compared to the desired protection mode. 14.3.5.22 Life cycle = SECURE (32) The life-cycle stage value is stored in eFuse.
Page 210 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture eFuse memory eFuse memory This PSoC™ 6 MCU reference manual provides comprehensive and detailed information about the functions of the PSoC™ 6 MCU device hardware. It is divided into two books: architecture reference manual and registers reference manual.
Page 211 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture eFuse memory Table 15-1. PSoC™ 6 MCU eFuse byte assignments (continued) Offset No. of Name Description bytes Unused Not used CUSTOM_DATA Custom data Reference manual 002-18176 Rev. *K 2023-07-26...
Page 212 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Device security Device security This PSoC™ 6 MCU reference manual provides comprehensive and detailed information about the functions of the PSoC™ 6 MCU device hardware. It is divided into two books: architecture reference manual and registers reference manual.
Page 213 • VIRGIN – This stage is used by Infineon during assembly and testing. During this stage, trim values and flash boot are written into SFlash. Devices that are in this stage never leave the factory. In this stage, the boot ROM assumes that no other eFuse data or flash data is valid.
Page 214 When invoking the system call to transition to RMA, the customer must provide a certificate that authorizes Infineon to transition the device with a specific Unique ID to the RMA life cycle stage. The certificate will be signed by the customer using the same private key that is used to sign the user application image. The verification of the signature uses the same algorithm used by flash boot to authenticate the user application.
Page 215 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Device security UNKNOWN (After Reset) VIRGIN eFuse Lifecycle Bits Set? NORMAL Lifecycle in NORMAL eFuse SECURE Lifecycle in SECURE eFuse Corruption or error detected during the boot process DEAD Figure 16-2. Protection state transitions Protection state is defined by the STATE field of the CPUSS_PROTECTION register.
Page 216 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Device security 16.2.2 Flash security PSoC™ 6 MCUs include a flexible flash-protection system that controls access to flash memory. This feature is designed to secure proprietary code, but it can also be used to protect against inadvertent writes to the bootloader portion of flash.
Page 217 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture System resources subsystem (SRSS) Section C: System resources subsystem (SRSS) This section encompasses the following chapters: • “Power supply and monitoring” on page 218 • “Device power modes” on page 227 •...
Page 218 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Power supply and monitoring Power supply and monitoring This PSoC™ 6 MCU reference manual provides comprehensive and detailed information about the functions of the PSoC™ 6 MCU device hardware. It is divided into two books: architecture reference manual and registers reference manual.
Page 219 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Power supply and monitoring 17.2 Architecture 10 µF 0.1 µF 1 µF 0.1 µF 1 µF 0.1 µF 1 µF 0.1 µF 1 µF 0.1 µF SS_NS DD_NS BACKUP DDIO SSIO PSoC™...
Page 220 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Power supply and monitoring In addition, the RF transceiver blocks in the Bluetooth® LE subsystem receives power from the V supply pin, DCDC which can be externally connected to the on-chip buck converter output (V ).
Page 221 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Power supply and monitoring Switching (Buck) core regulator The device includes a switching (buck) core regulator. The buck regulator included is a single input multiple (two) output (SIMO) regulator that can generate two outputs (V and V ) from a single input supply (V ).
Page 222 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Power supply and monitoring Core operating voltage PSoC™ 6 MCUs can operate at either 0.9 V LP mode (nominal) or 1.1 V ULP mode (nominal) core voltage. On reset, the core is configured to operate at 1.1 V by default. At 0.9 V, power consumption is less, but there are some limitations.
Page 223 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Power supply and monitoring 17.3.2 Power pins and rails Table 17-1 lists all the power supply pins available in the device. The supply rails running inside the device , and V ) are derived from these external supply pins/rails.
Page 224 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Power supply and monitoring 17.3.4 Backup domain The PSoC™ 6 MCU offers an independent backup supply option (V ). This rail powers a small set of BACKUP peripherals that includes an RTC, WCO, and a small number of retention registers. This rail is independent of all other rails and can exist even when other rails are absent.
Page 225 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Power supply and monitoring 17.4.3 Low-voltage-detect (LVD) An LVD circuit monitors external supply voltage and accurately detects depletion of the energy source. The LVD generates an interrupt to cause the system to take preventive measures. The LVD can be configured to monitor V , or V .
Page 226 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Power supply and monitoring PSoC™ 6 LVD block HVLVD1_EN HVLVD1_SRCSEL [2:0] AMUXA AMUXB HVLVD1 SRSS_INTR[HVLVD1] To CPU as SRSS interrupt 1.2 V SRSS_INTR_MASK[HVLVD1] 3.1 V HVLVD1_TRIPSEL [3:0] Figure 17-2. PSoC™ 6 MCU LVD block 17.4.4 Overvoltage protection (OVP) The PSoC™...
Page 227 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Device power modes Device power modes This PSoC™ 6 MCU reference manual provides comprehensive and detailed information about the functions of the PSoC™ 6 MCU device hardware. It is divided into two books: architecture reference manual and registers reference manual.
Page 228 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Device power modes The SysPm Peripheral Driver Library (PDL) driver supports all device power mode transitions and is the recommended method of transition and configuration of PSoC™ 6 MCU power resources. Table 18-1 summarizes the power modes available in PSoC™...
Page 229 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Device power modes Table 18-1. PSoC™ 6 MCU power modes (continued) System Description Entry conditions Wakeup Wakeup power power sources action mode mode Active 0.9 V core voltage. All Manual register write from peripherals are available system LP mode.
Page 230 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Device power modes 18.2.1 CPU power modes The CPU Active, Sleep, and Deep Sleep modes are the standard Arm®-defined power modes supported by both Cortex®-M4 and Cortex®-M0+ CPUs. All Arm® CPU power modes are available in both system LP and ULP power modes.
Page 231 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Device power modes 18.2.3 System Deep Sleep mode In system Deep Sleep mode, all the high-speed clock sources are off. This in turn makes high-speed peripherals unusable in system Deep Sleep mode. However, low-speed clock sources and peripherals may continue to operate, if configured and enabled by the firmware.
Page 232 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Device power modes some content. Note that these registers are reset by other reset events. On a Hibernate wakeup event, the HIBERNATE bit [31] of the PWR_HIBERNATE register is cleared. The brownout detect (BOD) block is not available in Hibernate mode. As a result, the device does not recover from a brownout event in Hibernate mode.
Page 233 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Device power modes 18.3 Power mode transitions Figure 18-1 shows various states the device can be in along with possible power mode transition paths. O ff X R E S /P O R / X R E S /P O R /B O D X R E S B O D...
Page 234 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Device power modes 18.3.1 Power-up transitions Table 18-2 summarizes various power-up transitions, their type, triggers, and actions. Table 18-2. Power mode transitions Initial Final Type Trigger Actions state state XRES External Power rail (V ) ramps up 1.
Page 235 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Device power modes 18.3.2 Power mode transitions Table 18-3. Power mode transitions Initial Final Type Trigger Actions state state System LP System Internal Firmware action 1. Device is put into 1. Ensure the Clk_HF paths, peripheral, and slow ULP mode with all clocks are less than the ULP clock speed limitations.
Page 236 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Device power modes Table 18-3. Power mode transitions (continued) Initial Final Type Trigger Actions state state System System Internal Firmware action 1. CPU clocks are LP/ULP LP/UP Perform these steps to enter Deep Sleep mode gated off and CPU and CPU...
Page 237 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Device power modes Table 18-3. Power mode transitions (continued) Initial Final Type Trigger Actions state state System System Internal Hardware action 1. High-frequency LP/ULP Deep 1. When both CPUs enter CPU Deep Sleep mode and clocks are shut down.
Page 238 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Device power modes 18.3.3 Wakeup transitions Table 18-4. Wakeup transitions Initial Final state Type Trigger Actions state CPU Sleep CPU Active Internal/ Any peripheral 1. Clock to CPU is ungated. External interrupt masked 2.
Page 239 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Device power modes 18.4 Summary Table 18-5. Resources available in different power modes Component Power modes Deep Sleep Hibernate XRES Power off with CPU Sleep/ CPU Sleep/ backup Active Deep Sleep Active Deep Sleep Core functions...
Page 240 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Device power modes Table 18-5. Resources available in different power modes (continued) Component Power modes Deep Sleep Hibernate XRES Power off with CPU Sleep/ CPU Sleep/ backup Active Deep Sleep Active Deep Sleep Backup domain WCO, RTC, alarms On...
Page 241 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Backup system Backup system This PSoC™ 6 MCU reference manual provides comprehensive and detailed information about the functions of the PSoC™ 6 MCU device hardware. It is divided into two books: architecture reference manual and registers reference manual.
Page 242 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Backup system 19.2 Architecture AHB-Lite Bus (Power Supply Pins) User Registers RTC Registers AHB Interface Backup DDBAK Power Switch BACKUP MMIO Alarm Alarm Interface Config Config PMIC_Wakeup_In Backup Watch Crystal PMIC_Wakeup_Out Registers Oscillator (32 bytes)
Page 243 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Backup system Note: If V and V are connected on the PCB, the Backup domain may require an explicit reset triggered BACKUP by firmware using the RESET bitfield in the BACKUP_RESET register. This firmware reset is required if the V supply was invalid during a previous power supply ramp-up or brownout event.
Page 244 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Backup system formed by connecting a 220-pF/6-V capacitor between WCO_IN and ground, and a 2.2-pF/ 200-V capacitor between WCO_IN and the 60-Hz/120-V mains input. The PRESCALER bitfield in BACKUP_CTL must be configured for a prescaler value of 60.
Page 245 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Backup system BCD encoding indicates that each four-bit nibble represents one decimal digit. Constant bits are omitted in the RTC implementation. For example, the maximum RTC_SEC is 59, which can be represented as two binary nibbles 0101b 1001b.
Page 246 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Backup system 19.7 Alarm feature The Alarm feature allows the RTC to be used to generate an interrupt, which may be used to wake up the system from Sleep, Deep Sleep, and Hibernate power modes. The Alarm feature consists of six fields corresponding to the fields of the RTC: Month/Date, Day-of-Week, and Hour : Minute : Second.
Page 247 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Backup system The BACKUP_INTR_MASK register can be used to disable certain interrupts from the backup system. Table 19-3. Interrupt mask bits Bit name Description ALARM1 Mask bit for interrupt generated by ALARM1 ALARM2 Mask bit for interrupt generated by ALARM2 CENTURY...
Page 248 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Backup system When the PMIC_EN bit is cleared by firmware, the external PMIC is disabled and the system functions normally until V is no longer present (OFF with Backup mode). The firmware can set this bit if it does so before V actually removed.
Page 249 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Clocking system Clocking system This PSoC™ 6 MCU reference manual provides comprehensive and detailed information about the functions of the PSoC™ 6 MCU device hardware. It is divided into two books: architecture reference manual and registers reference manual.
Page 250 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Clocking system 20.2 Architecture Figure 20-1 gives a generic view of the clocking system in PSoC™ 6 MCUs. Path Mux Root mux (FLL/PLL) clk_fast (CM4) CLK_HF[0] Predivider (1/2/4/8) clk_slow dsi_in0 clk_peri (CM0) EXTCLK Predivider...
Page 251 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Clocking system 20.3.2.1 ECO trimming The ECO supports a wide variety of crystals and ceramic resonators with the nominal frequency range specification of f = 16 MHz – 35 MHz. The crystal manufacturer typically provides numerical values for parameters, namely the maximum drive level (DL), the equivalent series resistance (ESR), shunt capacitance of the crystal (C and the parallel load capacitance (C ).
Page 252 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Clocking system 20.3.4 Alternate high-frequency clock (ALTHF) ALTHF is an alternate high-frequency clock. This clock is generated outside of the clocking system described in this chapter. For PSoC™ 63, this clock is the ECO that is connected to the Bluetooth® LE subsystem. The ALTHF path allows routing the Bluetooth®...
Page 253 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Clocking system Periodic calibration to a high-accuracy clock (such as ECO) is required to maintain accuracy. The calibration counters described in “Clock calibration counters” on page 267 can be used to measure the PILO against a high- accuracy clock such as the ECO.
Page 254 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Clocking system 3. Enable the PLL (CLK_PLL_CONFIG.ENABLE = 1). Wait at least 1 µs for PLL circuits to start. 4. Wait until the PLL is locked before using the output. By default, the PLL output is bypassed to its reference clock and will automatically switch to the PLL output when it is locked.
Page 255 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Clocking system If the FLL counts a value different from 1825, it attempts to adjust the CCO such that it achieves 1825 the next time it counts. This is done by scaling the error term with FLL_LF_IGAIN and FLL_LF_PGAIN found in CLK_FLL_CONFIG3.
Page 256 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Clocking system 20.4.2.1 Configuring the FLL This section provides a guide to calculate FLL parameters. The following equations are tailored to achieve the best accuracy. In these equations: N = REF_DIV M = FLL _MULT 1.
Page 257 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Clocking system To determine the values for I and P use the following equation: GAIN GAIN     0.85   ---------------------------- -  GAIN    ------- - ...
Page 258 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Clocking system 2. Set CCO_FREQ in CLK_FLL_CONFIG4. This field determines the frequency at which the FLL starts before any measurement. The nearer the FLL is to the desired frequency, the faster it will lock. ...
Page 259 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Clocking system 4. Write CLK_FLL_CONFIG3.BYPASS_SEL = FLL_OUT to switch to the FLL output. To disable the FLL, follow these steps: 1. Ensure the processor is operating from a different clock than clk_path0. If the muxes are changed, wait four FLL output clock cycles for it to complete.
Page 260 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Clocking system The DSI mux is configured through the CLK_DSI_SELECT[i] register. Table 20-10. DSI Mux source selection Name Description PATH_MUX[2:0] Selects the source for the DSI_MUX[i] 0: dsi_out[0] 1: dsi_out[1] 2-15: Reserved 16: ILO 17: WCO 18: Reserved...
Page 261 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Clocking system CLK_HF[1-4] can be enabled and disabled. CLK_HF[0] is always enabled as it is the source of the CPU. To enable and disable CLK_HF[1-4] set the ENABLE bit in the CLK_ROOT_SELECT register. 20.5.3 Low-frequency clock The low-frequency clock (CLK_LF) in the PSoC™...
Page 262 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Clocking system 20.6 CLK_HF[0] distribution clk_hf[0] is the root clock for the CPU subsystem and for the peripheral clock dividers. Predivider CLK_HF[0] CLK_FAST 1-256 Predivider Predivider CM0+ CLK_PERI CLK_SLOW 1-256 1-256 To peripheral clock dividers Figure 20-4.
Page 263 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Clocking system Fractional dividers are useful when a high-precision clock is required (for example, for a UART/SPI serial interface). Fractional dividers are not used when a low jitter clock is required, because the clock periods have a jitter of one CLK_PERI cycle.
Page 264 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Clocking system Phase alignment CLK_PERI (48 MHz) 24 MHz gated clock 12 MHz gated clock Figure 20-6. Phase-aligned clock dividers Phase alignment also works for fractional divider values. If (enabled) divider x is used to generate the 38.4-MHz clock (divide by 1 8/32), divider y can be phase-aligned to divider x and used to generate the 19.2-MHz clock (divide by 2 16/32).
Page 265 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Clocking system 20.7.2.2 Connecting dividers to peripheral The PSoC™ 6 MCU has 58 peripherals, which can connect to one of the programmable dividers. Table 20-15 lists those peripherals. Table 20-15. PSoC™ 6 MCU clock dividers to peripherals Clock number Destination scb[0].clock...
Page 266 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Clocking system Table 20-15. PSoC™ 6 MCU clock dividers to peripherals (continued) Clock number Destination tcpwm[1].clocks[8] tcpwm[1].clocks[9] tcpwm[1].clocks[10] tcpwm[1].clocks[11] tcpwm[1].clocks[12] tcpwm[1].clocks[13] tcpwm[1].clocks[14] tcpwm[1].clocks[15] tcpwm[1].clocks[16] tcpwm[1].clocks[17] tcpwm[1].clocks[18] tcpwm[1].clocks[19] tcpwm[1].clocks[20] tcpwm[1].clocks[21] tcpwm[1].clocks[22] tcpwm[1].clocks[23] csd.clock lcd.clock Reserved...
Page 267 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Clocking system 20.8 Clock calibration counters A feature of the clocking system in PSoC™ 6 MCUs is built-in hardware calibration counters. These counters can be used to compare the frequency of two clock sources against one another. The primary use case is to take a higher accuracy clock such as the ECO and use it to measure a lower accuracy clock such as the ILO or PILO.
Page 268 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Reset system Reset system This PSoC™ 6 MCU reference manual provides comprehensive and detailed information about the functions of the PSoC™ 6 MCU device hardware. It is divided into two books: architecture reference manual and registers reference manual.
Page 269 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Reset system Table 21-1 lists all the reset sources in the PSoC™ 6 MCU. Table 21-1. PSoC™ 6 MCU reset sources Reset source Reset condition Availability in Cause detection system power modes Power-on reset This reset condition occurs during...
Page 270 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Reset system 21.2.1 Power-on reset Power-on reset is provided to keep the system in a reset state during power-up. POR holds the device in reset until the supply voltage, V reaches the datasheet specification. The POR activates automatically at power-up. See the device datasheet for details on the POR trip-point levels.
Page 271 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Reset system 21.2.6 Logic protection fault reset Logic protection fault reset detects any unauthorized protection violations and causes the device to reset if they occur. One example of a protection fault is reaching a debug breakpoint while executing privileged code. The RESET_ACT_FAULT or RESET_DPSLP_FAULT bits of the RES_CAUSE register is set when a protection fault occurs in Active or Deep Sleep modes, respectively.
Page 272 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Reset system Table 21-2. Reset cause bits to detect reset source (continued) Register Bitfield Number Description of bits RES_CAUSE RESET_DPSLP_FAULT Fault logging system requested a reset from its Deep Sleep logic. RES_CAUSE RESET_CSV_WCO_LOSS 1 Clock supervision logic requested a reset due to loss of a...
Page 273 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture I/O system I/O system This PSoC™ 6 MCU reference manual provides comprehensive and detailed information about the functions of the PSoC™ 6 MCU device hardware. It is divided into two books: architecture reference manual and registers reference manual.
Page 274 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture I/O system 22.2 Architecture The PSoC™ 6 MCU is equipped with analog and digital peripherals. Figure 22-1 shows an overview of the routing between the peripherals and pins. GPIO & Port UDB Array Control Fixed Function...
Page 275 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture I/O system 22.2.1 I/O cell architecture Figure 22-2 shows the I/O cell architecture present in every GPIO cell. It comprises an input buffer and an output driver that connect to the HSIOM multiplexers for digital input and output signals. Analog peripherals connect directly to the pin for point to point connections or use the AMUXBUS.
Page 276 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture I/O system 22.2.2 Digital input buffer The digital input buffer provides a high-impedance buffer for the external digital input. The buffer is enabled or disabled by the IN_EN[7:0] bit of the Port Configuration Register (GPIO_PRTx_CFG, where x is the port number). The input buffer is connected to the HSIOM for routing to the CPU port registers and selected peripherals.
Page 277 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture I/O system Table 22-1. Drive mode settings Drive mode Value CPU Register, AMUXBUS, UDB/DSI Fixed-function digital peripheral digital peripheral OUT_EN = 1 OUT_EN = 0 OUT_EN = 1 OUT_EN = 0 OUT = 1 OUT = 0 OUT = 1 OUT = 0 OUT = 1 OUT = 0 OUT = 1 OUT = 0 High impedance HI-Z...
Page 278 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture I/O system DDIO DDIO DDIO OUT_EN OUT_EN OUT_EN OUT_EN High Impedance Reserved Resistive Resistive Pull up Pull down DDIO DDIO DDIO DDIO OUT_EN OUT_EN OUT_EN OUT_EN Open Drain, Open Drain, Strong Resistive Pull Up Drives Low Drives High...
Page 279 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture I/O system • Resistive pull-up and resistive pull-down In the resistive pull-up and pull-down mode, the GPIO will have a series resistance in both logic 1 and logic 0 output states. The high data state is pulled up while the low data state is pulled down. This mode is useful when the pin is driven by other signals that may cause shorts.
Page 280 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture I/O system Table 22-2. HSIOM connections (continued) SELy_SEL Name Digital driver signal Digital input Analog Description source signal switches destination OUT_EN AMUX AMUX DSI_GPIO DSI OUT DSI IN DSI controls OUT, Register GPIO_PRTx_OUT register controls OUT_EN...
Page 281 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture I/O system Table 22-2. HSIOM connections (continued) SELy_SEL Name Digital driver signal Digital input Analog Description source signal switches destination OUT_EN AMUX AMUX DS_3 Deep Deep Sleep Deep Sleep Deep Sleep functionality 3 - Sleep Source See the datasheet for specific...
Page 282 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture I/O system Table 22-2. HSIOM connections (continued) SELy_SEL Name Digital driver signal Digital input Analog Description source signal switches destination OUT_EN AMUX AMUX DS_4 Deep Deep Sleep Deep Sleep Deep Sleep functionality 4 - Sleep Source See the datasheet for specific...
Page 283 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture I/O system 22.5 Behavior in low-power modes Table 22-3 shows the status of GPIOs in low-power modes. Table 22-3. GPIO in low-power modes Low-power Status mode • Standard GPIO, GPIO-OVT, and SIO pins are active and can be driven by most peripherals CPU Sleep such as CAPSENSE™, TCPWMs, and SCBs, which can operate in CPU Sleep mode.
Page 284 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture I/O system Edge Detector 50 ns Glitch Filter Pin 0 Edge Detector Pin 1 Edge Detector Pin 2 Edge Detector Pin 3 Edge Detector Interrupt Signal Pin 4 Edge Detector Pin 5 Edge Detector Pin 6 Edge Detector...
Page 285 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture I/O system When a port pin edge occurs, you can read the Port Interrupt Status register, GPIO_PRTx_INTR, to know which pin caused the edge. This register includes both the latched information on which pin detected an edge and the current pin status.
Page 286 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture I/O system 22.8.2 Analog I/O Analog resources, such as LPCOMP, SAR ADC, and CTB, which require low-impedance routing paths have dedicated pins. Dedicated analog pins provide direct connections to specific analog blocks. They help improve performance and should be given priority over other pins when using these analog resources.
Page 287 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture I/O system 22.9 Smart I/O The Smart I/O block adds programmable logic to an I/O port. This programmable logic integrates board-level Boolean logic functionality such as AND, OR, and XOR into the port. The Smart I/O block has these features: •...
Page 288 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture I/O system 22.9.2.1 Clock and reset The clock and reset component selects the Smart I/O block’s clock (clk_block) and reset signal (rst_block_n). A single clock and reset signal is used for all components in the block. The clock and reset sources are determined by the CLOCK_SRC[4:0] bitfield of the SMARTIO_PRTx_CTL register.
Page 289 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture I/O system Table 22-6. Clock and Reset Register control Register[BIT_POS] Bit name Description SMARTIO_PRTn_CTL[ CLOCK_SRC[4:0] Clock (clk_block)/reset (rst_block_n) source selection: 12:8] 0: io_data_in[0]/1 7: io_data_in[7]/1 8: chip_data[0]/1 15: chip_data[7]/1 16: clk_smartio/rst_sys_act_n; asserts reset in any power mode other than System LP or ULP;...
Page 290 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture I/O system 22.9.2.3 Lookup table (LUT) Each Smart I/O block contains eight lookup table (LUT) components. The LUT component consists of a three- input LUT and a flip-flop. Each LUT block takes three input signals and generates an output based on the configuration set in the SMARTIO_PRTx_LUT_CTLy register (y denotes the LUT number).
Page 291 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture I/O system Table 22-7. LUT Register control (continued) Register[BIT_POS] Bit name Description SMARTIO_PRTx_LUT_SELy[3:0] LUT_TR0_SEL[3:0] LUT input signal “tr0_in” source selection: 0: Data unit output 1: LUT 1 output 2: LUT 2 output 3: LUT 3 output 4: LUT 4 output 5: LUT 5 output...
Page 292 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture I/O system Table 22-7. LUT Register control (continued) Register[BIT_POS] Bit name Description SMARTIO_PRTx_LUT_SELy[11:8] LUT_TR1_SEL[3:0] LUT input signal “tr1_in” source selection: 0: LUT 0 output 1: LUT 1 output 2: LUT 2 output 3: LUT 3 output 4: LUT 4 output 5: LUT 5 output...
Page 293 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture I/O system OPC[1:0] = 0 tr0_in tr1_in tr_out tr2_in LUT[7:0] OPC[1:0] = 1 tr0_in tr1_in tr_out tr2_in clk_block LUT[7:0] OPC[1:0] = 2 tr0_in tr1_in tr_out tr2_in clk_block LUT[7:0] OPC[1:0] = 3 LUT[5] Enable LUT[4]...
Page 294 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture I/O system The trigger signals are selected using the DU_TRx_SEL[3:0] bitfield of the SMARTIO_PRTx_DU_SEL register. The DUT_DATAx_SEL[1:0] bits of the SMARTIO_PRTx_DU_SEL register select the 8-bit input data source. The size of the DU (number of bits used by the datapath) is defined by the DU_SIZE[2:0] bits of the SMARTIO_PRTx_DU_CTL register.
Page 295 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture I/O system mask = (2 ^ (DU_SIZE+1) – 1) data_eql_data1_in = (data & mask) == (data1_in & mask)); data_eql_0 = (data & mask) == 0); data_incr = (data + 1) & mask; data_decr = (data - 1) &...
Page 296 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture I/O system else if (tr1_in) data <= data_eql_data1_in ? data0_masked : data_incr; else if (tr2_in) data <= data_eql_0 ? data0_masked : data_decr; // ROR operation: rotates data right and LSb is sent out. The data for rotation is taken from // data0.
Page 297 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture I/O system if (tr0_in) data <= data0_masked; 22.9.3 Routing The Smart I/O block includes many switches that are used to route the signals in and out of the block and also between various components present inside the block.
Page 298 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture I/O system b) Pipelined trigger mode: The LUT input multiplexers and the LUT component itself do not include any combinatorial loops. Similarly, the data unit also does not include any combinatorial loops. However, when one LUT interacts with the other or to the data unit, inadvertent combinatorial loops are possible.
Page 299 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture I/O system 22.10 Registers Table 22-10. I/O Registers Name Description GPIO_PRTx_OUT Port output data register reads and writes the output driver data for I/O pins in the port. GPIO_PRTx_OUT_CLR Port output data clear register clears output data of specific I/O pins in the port. GPIO_PRTx_OUT_SET Port output data set register sets output data of specific I/O pins in the port.
Page 300 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Watchdog timer Watchdog timer This PSoC™ 6 MCU reference manual provides comprehensive and detailed information about the functions of the PSoC™ 6 MCU device hardware. It is divided into two books: architecture reference manual and registers reference manual.
Page 301 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Watchdog timer Device Interrupt CFG/STATUS Registers Free running watchdog timer Clock Reset CFG/STATUS Interrupt Multi counter watchdog timers (x2) Device Reset frequency Clock clock (LFCLK) Reset Figure 23-1. Watchdog timer block diagram 23.3 Free-running WDT 23.3.1...
Page 302 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Watchdog timer When enabled, the WDT counts up on each rising edge of the ILO. When the counter value (WDT_CNT register) equals the match value stored in MATCH bits [15:0] of the WDT_MATCH register, an interrupt is generated. The match event does not reset the WDT counter and the WDT keeps counting until it reaches the 16-bit boundary (65535) at which point, it wraps around to 0 and counts up.
Page 303 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Watchdog timer Table 23-1. Free-running WDT configuration options (continued) Register [Bit_Pos] Bit_Name Description SRSS_INTR[0] WDT_MATCH WDT interrupt request This bit is set whenever a watchdog match event happens. The WDT interrupt is cleared by writing a ‘1’ to this bit SRSS_INTR_MASK[0] WDT_MATCH Mask for the WDT interrupt 0: WDT interrupt is blocked...
Page 304 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Watchdog timer 23.3.3 Watchdog interrupt In addition to generating a device reset, the WDT can be used to generate interrupts. Note that interrupt servicing and watchdog reset cannot be used simultaneously using the free-running WDT. The watchdog counter can send interrupt requests to the CPU in CPU Active power modes and to the wakeup interrupt controller (WIC) in CPU Sleep and Deep Sleep power modes.
Page 305 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Watchdog timer 23.4 Multi-counter WDTs 23.4.1 Overview Figure 23-3 shows the functional overview of a single multi-counter WDT block. The PSoC™ 6 MCU has two MCWDT blocks. Each MCWDT block includes two 16-bit counters (MCWDTx_WDT0 and MCWDTx_WDT1) and one 32-bit counter (MCWDTx_WDT2).
Page 306 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Watchdog timer 23.4.1.1 MCWDTx_WDT0 and MCWDTx_WDT1 counters operation MCWDTx_WDT0 and MCWDTx_WDT1 are 16-bit up counters, which can be configured to be a 16-bit free-running counter or a counter with any 16-bit period. These counters can be used to generate an interrupt or reset. The WDT_CTR0 bits [15:0] and WDT_CTR1 bits [16:31] of the MCWDTx_CNTLOW register hold the current counter values of MCWDTx_WDT0 and MCWDTx_WDT1 respectively.
Page 307 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Watchdog timer Table 23-2. MCWDTx_WDT0 and MCWDTx_WDT1 configuration options Register [Bit_Pos] Bit_Name Description MCWDTx_CONFIG[1:0] WDT_MODE0 WDT action on a match event (WDT_CTRx == WDT_MATCHx) MCWDTx_CONFIG[9:8] WDT_MODE1 0: Do nothing 1: Assert interrupt (WDT_INTx) 2: Assert device reset 3: Assert interrupt on match and a device reset on the third unhandled interrupt...
Page 308 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Watchdog timer 23.4.1.2 MCWDTx_WDT2 counter operation The MCWDTx_WDT2 is a 32-bit free-running counter, which can be configured to generate an interrupt. The MCWDTx_CNTHIGH register holds the current value of the MCWDTx_WDT2 counter. MCWDTx_WDT2 does not support a match feature.
Page 309 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Watchdog timer 23.4.2 Enabling and disabling WDT The MCWDT counters are enabled by setting the WDT_ENABLEx bit in the MCWDTx_CTL register and are disabled by clearing it. Enabling or disabling a MCWDT requires 1.5 LFCLK cycles to come into effect. Therefore, the WDT_ENABLEx bit value must not be changed more than once in that period and the WDT_ENABLEDx bit of the MCWDTx_CTL register can be used to monitor enabled/disabled state of the counter.
Page 310 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Watchdog timer 23.4.3 Watchdog cascade options The cascade configuration shown in Figure 23-3 provides an option to increase the MCWDT counter resolution. The WDT_CASCADE0_1 bit [3] of the MCWDTx_CONFIG register cascades MCWDTx_WDT0 and MCWDTx_WDT1 and the WDT_CASCADE1_2 bit [11] of the MCWDTx_CONFIG register cascades MCWDTx_WDT1 and MCWDTx_WDT2.
Page 311 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Watchdog timer LFCLK WDT_RESET0 First reset Second reset to issued to correct the both behavior counters WDT_RESET1 ~100 µs 0x001F 0x0020 0x0000 0x0001 0x0002 0x0003 0x0004 0x0005 WDT_CTR0 WDT_CTRx == WDT_MATCHx 0x0000 0x0001 0x0000...
Page 312 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Watchdog timer 23.4.4 MCDWT reset MCWDTx_WDT0 and MCWDTx_WDT1 can be configured to generate a device reset similar to the free-running WDT reset. Note that when the debug probe is connected, the device reset is blocked but an interrupt is generated if configured.
Page 313 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Watchdog timer 6. Enable WDTx by setting the WDT_ENABLEx bit in the MCWDTx_CTL register. Wait until the WDT_ENABLEDx bit is set. 7. Enable MCWDTx interrupt to the CPU by configuring the appropriate ISER register. See the “Interrupts”...
Page 314 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Trigger multiplexer block Trigger multiplexer block This PSoC™ 6 MCU reference manual provides comprehensive and detailed information about the functions of the PSoC™ 6 MCU device hardware. It is divided into two books: architecture reference manual and registers reference manual.
Page 315 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Trigger multiplexer block 24.2.1 Trigger multiplexer group The trigger multiplexer block is implemented using several trigger multiplexers. A trigger multiplexer selects a signal from a set of trigger output signals from different peripheral blocks to route it to a specific trigger input of another peripheral block.
Page 316 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Trigger multiplexer block Reduction Intermediate Distribution Trigger Multiplexer Trigger Multiplexer Multiplexer Group Signals Multiplexer Group Inputs Outputs Trigger Group 0 Trigger Group N Block_TR_OUT_TRIG_GRP0 [0:n] Block_TR_IN_TRIG_GRP0 [0:m] TR_OUT_TRIG_GRP0 [0:k] Trigger Group 1 Trigger Group N+1 Block_TR_OUT_TRIG_GRP1 [0:n] TR_OUT_TRIG_GRP1 [0:k]...
Page 317 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Trigger multiplexer block 24.2.4 Software triggers All input and output signals to a trigger multiplexer can be triggered from software. This is accomplished by writing into the PERI_TR_CMD register. This register allows you to trigger the corresponding signal for a number of peripheral clock cycles.
Page 318 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Trigger multiplexer block 24.4 Register list Table 24-1. Register list Register name Description PERI_TR_CMD Trigger command register. The control enables software activation of a specific input trigger or output trigger of the trigger multiplexer structure.
Page 319 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Trigger multiplexer block SW Input Cpuss.zero[0] Trigger Group 9 Tr_dw_ack[0:7] [1:16] Tr_out[0:15] DMA Burstend[0:7] Trigger Group 0 [17:32] Tr_out[0:15] [1:8] [9:24] Tr_in[0:15] [25:26] [27:42] [43:50] Trigger Group 10 Trigger Group 1 [0:7] [1:16] [1:8]...
Page 320 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Profiler Profiler This PSoC™ 6 MCU reference manual provides comprehensive and detailed information about the functions of the PSoC™ 6 MCU device hardware. It is divided into two books: architecture reference manual and registers reference manual.
Page 321 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Profiler 25.2 Architecture interrupt AHB Interface and MIMO Registers AHB Bus clk_hlf Profiling Counter units Counter Unit x1~x32 monitor signals clocks for counting cycle window start/stop triggers Figure 25-1. Profiler block diagram The profiler supports up to 32 counters.
Page 322 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Profiler Before starting a profiling session, configure the counters you want to use. See “Configure and enable a counter” on page 324. You can get interim results during a profiling session, or final results after you stop profiling. See “Get the results”...
Page 323 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Profiler 25.2.3 Reference clocks Each monitored source has its own clock reference, called the sample clock. Table 25-2 lists the six choices for the sample clock. You may use one of two CLK_PROFILE sources, or one of four CLK_REF sources. The counter units of the profiler are clocked using either CLK_HF or CLK_PERI as CLK_PROFILE.
Page 324 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Profiler You can monitor as many sources as there are available counters. The actual number of available counters is hardware dependent. The value is defined in the symbol PROFILE_PRFL_CNT_NR in the <series>_config.h file. For example, the psoc63_config.h file defines this value as ‘8’.
Page 325 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Profiler 25.3.3 Start and stop profiling After configuring and enabling the counters you want to use, you can start and stop a profiling session. You may wish to ensure that all counters are set to zero before beginning the profiling session. The PROFILE_CMD register applies to all counters, meaning that all enabled counters will be started at the same time.
Page 326 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Profiler 25.3.6 Exit gracefully When finished, you should disable the profiler. To do this make sure that you: • Stop profiling (see “Start and stop profiling” on page 325) • Clear any profiling configuration (see “Configure and enable a counter”...
Page 327 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Digital subsystem Section D: Digital subsystem This section encompasses the following chapters: • “Serial Communications Block (SCB)” on page 329 • “Serial memory interface (SMIF)” on page 394 • “Timer, Counter, and PWM (TCPWM)” on page 412 •...
Page 328 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Digital subsystem Top level architecture Digital system block diagram Programmable Digital: 12x UDB Color Key: Power Modes and Domains System LP/ULP Mode Audio Subsystem CPUs Active/Sleep System DeepSleep Mode System Hibernate Mode Backup Domain Reference manual...
Page 329 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Serial Communications Block (SCB) Serial Communications Block (SCB) This PSoC™ 6 MCU reference manual provides comprehensive and detailed information about the functions of the PSoC™ 6 MCU device hardware. It is divided into two books: architecture reference manual and registers reference manual.
Page 330 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Serial Communications Block (SCB) 26.2 Architecture The operation modes supported by SCB are described in the following sections. 26.2.1 Buffer modes Each SCB has 256 bytes of dedicated RAM for transmit and receive operation. This RAM can be configured in three different modes (FIFO, EZ, or CMD_RESP).
Page 331 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Serial Communications Block (SCB) 26.2.2 Clocking modes The SCB can be clocked either by an internal clock provided by the peripheral clock dividers (referred to as clk_scb in this document), or it can be clocked by the external master. •...
Page 332 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Serial Communications Block (SCB) 26.3 Serial peripheral interface (SPI) The SPI protocol is a synchronous serial interface protocol. Devices operate in either master or slave mode. The master initiates the data transfer. The SCB supports single-master-multiple-slaves topology for SPI. Multiple slaves are supported with individual slave select lines.
Page 333 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Serial Communications Block (SCB) 26.3.2 General description Figure 26-1 illustrates an example of SPI master with four slaves. SCLK MOSI MISO Slave 1 Master Slave Select (SS) 1 Slave 2 Slave Select (SS) 2 Slave 3 Slave Select (SS) 3 Slave 4...
Page 334 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Serial Communications Block (SCB) By default, the SPI interface supports a data frame size of eight bits (1 byte). The data frame size can be configured to any value in the range 4 to 16 bits. The serial data can be transmitted either most significant bit (MSb) first or least significant bit (LSb) first.
Page 335 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Serial Communications Block (SCB) CPOL = 0 CPHA = 0 SCLK MISO / MOSI CPOL = 0 CPHA = 1 SCLK MISO / MOSI CPOL = 1 CPHA = 0 SCLK MISO / MOSI CPOL = 1...
Page 336 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Serial Communications Block (SCB) CPHA = 0, CPOL = 0 Oversampling = 5 (1 SCLK period contains 6 clk_scb periods) clk_scb SCLK ¼ SCLK ¾ SCLK CPHA = 1, CPOL = 0 Oversampling = 5 (1 SCLK period contains 6 clk_scb periods) clk_scb SCLK...
Page 337 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Serial Communications Block (SCB) single data transfer CPOL=0, CPHA=1 SCLK MOSI MISO two successive data transfers CPOL=0, CPHA=1 SCLK LSb MSb MOSI MISO LSb MSb Figure 26-5. SPI TI data transfer example Figure 26-6 illustrates a single 8-bit data transfer and two successive 8-bit data transfers.
Page 338 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Serial Communications Block (SCB) Configuring SCB for SPI TI mode To configure the SCB for SPI TI mode, set various register bits in the following order: 1. Select SPI by writing ‘01’ to the MODE (bits [25:24]) of the SCB_CTRL register. 2.
Page 339 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Serial Communications Block (SCB) Configuring SCB for SPI NS mode To configure the SCB for SPI NS mode, set various register bits in the following order: 1. Select SPI by writing ‘01’ to the MODE (bits [25:24]) of the SCB_CTRL register. 2.
Page 340 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Serial Communications Block (SCB) Note: Before going into deep sleep the wakeup interrupt should be cleared. See the “SPI interrupts” page 385 for more details. Deep Sleep to Active transition EC_AM = 1, EC_OP = 0, FIFO mode. When the SPI Slave Select line is asserted the device will be awoken by an interrupt.
Page 341 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Serial Communications Block (SCB) Memory Array Write A write to a memory array index starts with a command byte (0x01) on the MOSI line indicating the master’s intent to write to the memory array. The slave then drives a reply byte on the MISO line to indicate that the command was registered (0xFE) or not (0xFF).
Page 342 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Serial Communications Block (SCB) Command 0x00 : Write EZ address SCLK Command 0x00 EZ Address MOSI MISO EZ address (8 bits) EZ address Command 0x01 : Write DATA SCLK Write DATA Command 0x01 MOSI MISO...
Page 343 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Serial Communications Block (SCB) For more information on these registers, see the registers reference manual. Active to Deep Sleep transition Before going to deep sleep ensure the master is not currently transmitting to the slave. This can be done by checking the BUS_BUSY bit in the SPI_STATUS register.
Page 344 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Serial Communications Block (SCB) the slave’s base read address. Transmitted data elements are read from the current address memory location. After each read data element is transferred, the current read address is incremented. During the reception of the first byte, the slave (MISO) transmits either 0x62 (ready) or a value different from 0x62 (busy).
Page 345 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Serial Communications Block (SCB) Configuring SCB for CMD_RESP mode By default, the SCB is configured for non-CMD_RESP mode of operation. To configure the SCB for CMD_RESP mode, set the register bits in the following order: 1.
Page 346 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Serial Communications Block (SCB) • EC_AM_MODE is ‘1’ and EC_OP_MODE is ‘1’. Use this mode when both Active and Deep Sleep functionality are required. When the slave is selected, INTR_SPI_EC.WAKE_UP is set to ‘1’. The associated Deep Sleep functionality interrupt brings the system into Active power mode.
Page 347 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Serial Communications Block (SCB) 26.3.5.2 Using SPI master to clock slave In a normal SPI Master mode transmission, the SCLK is generated only when the SCB is enabled and data is being transmitted.
Page 348 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Serial Communications Block (SCB) spi_ select CPOL : 0 , CPHA : 0 spi_clk spi_ mosi spi_ miso late MISO sample normal MISO sample Figure 26-11. MISO sampling timing This changes the equation to: ...
Page 349 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Serial Communications Block (SCB) operation mode (from Motorola mode to TI mode) or to go from externally clocked to internally clocked operation. The change takes effect only after the block is re-enabled. Note: Re-enabling the block causes re-initialization and the associated state is lost (for example, FIFO content).
Page 350 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Serial Communications Block (SCB) 26.3.7.2 SPI slave Figure 26-13 Table 26-5 list the use of I/O pads for SPI slave. spi_clk_out_en spi_ctl don t care spi_clk_out spi_clk spi_clk_in spi_clk_in Input only spi_select_out_en spi_ctl don t care...
Page 351 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Serial Communications Block (SCB) 26.3.7.3 Glitch avoidance at system reset The SPI outputs are in high-impedance digital state when the device is coming out of system reset. This can cause glitches on the outputs. This is important if you are concerned with SPI master SS0 – SS3 or SCLK output pins activity at either device startup or when coming out of Hibernate mode.
Page 352 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Serial Communications Block (SCB) Table 26-6. SPI Registers (continued) Register name Operation SCB_TX_FIFO_STATUS Indicates the number of bytes stored in the transmitter FIFO, the location from which a data frame is read by the hardware (read pointer), the location from which a new data frame is written (write pointer), and decides whether the transmitter FIFO holds the valid data.
Page 353 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Serial Communications Block (SCB) 26.4.2 General description Figure 26-14 illustrates a standard UART TX and RX. UART UART Figure 26-14. UART example A typical UART transfer consists of a start bit followed by multiple data bits, optionally followed by a parity bit and finally completed by one or more stop bits.
Page 354 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Serial Communications Block (SCB) Two successive data transfers (7data bits, 1 parity bit, 2 stop bits) Tx / Rx STOP START START DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA IDLE LEGEND:...
Page 355 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Serial Communications Block (SCB) Parity This functionality adds a parity bit to the data frame and is used to identify single-bit data frame errors. The parity bit is always directly after the data frame bits. The transmitter calculates the parity bit (when UART_TX_CTRL.PARITY_ENABLED is 1) from the data frame bits, such that data frame bits and parity bit have an even (UART_TX_CTRL.PARITY is 0) or odd (UART_TX_CTRL.PARITY is 1) parity.
Page 356 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Serial Communications Block (SCB) uart_rx IDLE/STOP START START Active Active power mode A -> DS Deep Sleep DS -> A UART not operational UART RX synchronizes CPU enables Rx functionality UART Rx Setup IOSS/GPIO IOSS/GPIO wake up interrupt synchronizes...
Page 357 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Serial Communications Block (SCB) Flow control The standard UART mode supports flow control. Modem flow control controls the pace at which the transmitter transfers data to the receiver. Modem flow control is enabled through the UART_FLOW_CTRL.CTS_ENABLED register field.
Page 358 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Serial Communications Block (SCB) The main properties of UART_MP mode are: • Single master with multiple slave concept (multi-drop network). • Each slave is identified by a unique address. • Using 9-bit data field, with the ninth bit as address/data flag (MP bit). When set high, it indicates an address byte;...
Page 359 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Serial Communications Block (SCB) LIN Master 1 LIN Slave 1 LIN Slave 2 UART LIN UART LIN UART LIN LIN Transceiver LIN Transceiver LIN Transceiver LIN BUS Figure 26-24. UART_LIN and LIN transceiver LIN protocol defines two tasks: •...
Page 360 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Serial Communications Block (SCB) In LIN protocol communication, the least significant bit (LSb) of the data is sent first and the most significant bit (MSb) last. The start bit is encoded as zero and the stop bit is encoded as one. The following sections describe all the byte fields in the LIN frame.
Page 361 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Serial Communications Block (SCB) • Enhanced checksum: the checksum calculated over all the data bytes along with the protected identifier (used in LIN 2.x slaves). LIN frame types The type of frame refers to the conditions that need to be valid to transmit the frame. According to the LIN specification, there are five different types of LIN frames.
Page 362 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Serial Communications Block (SCB) This behavior is application specific. The LIN slave nodes automatically enter Sleep mode if the LIN bus inactivity is more than four seconds. Wake-up can be initiated by any node connected to the LIN bus – either LIN master or any of the LIN slaves by forcing the bus to be dominant for 250 µs to 5 ms.
Page 363 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Serial Communications Block (SCB) Configuring SCB as UART SmartCard interface To configure the SCB as a UART SmartCard interface, set various register bits in the following order; note that ModusToolbox™ does all this automatically with the help of GUIs. For more information on these registers, see registers reference manual.
Page 364 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Serial Communications Block (SCB) 26.4.4 Clocking and oversampling The UART protocol is implemented using clk_scb as an oversampled multiple of the baud rate. For example, to implement a 100-kHz UART, clk_scb could be set to 1 MHz and the oversample factor set to ‘10’. The oversampling is set using the SCB_CTRL.OVS register field.
Page 365 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Serial Communications Block (SCB) 26.4.6 I/O pad connection 26.4.6.1 Standard UART mode Figure 26-32 Table 26-7 list the use of the I/O pads for the Standard UART mode. uart_tx_ctl uart_tx_out_en uart_tx_out uart_tx_out uart_tx uart_tx_in...
Page 366 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Serial Communications Block (SCB) Table 26-8. SmartCard mode I/O pad connections I/O pads Drive mode On-chip I/O Usage signals uart_tx Open drain uart_tx_in Used to receive a data element. with pull-up Receive a negative acknowledge-ment of a transmitted data element uart_tx_out_en...
Page 367 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Serial Communications Block (SCB) 26.4.6.4 IrDA mode Figure 26-35 Table 26-10 list the use of the I/O pads for IrDA mode. uart_tx_out_en uart_tx_ctl Normal uart_tx_out uart_tx_out output mode IrDA uart_tx uart_tx_in uart_tx_in transducer module...
Page 368 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Serial Communications Block (SCB) 26.5 Inter integrated circuit (I This section explains the I C implementation in the PSoC™ 6 MCU. For more information on the I C protocol specification, see the I C-bus specification available on the website.
Page 369 ) are primarily determined by the supply voltage, bus speed, and bus capacitance. For detailed information on how to calculate the optimum pull-up resistor value for your design Infineon recommends using the UM10204 I C-bus specification and user manual Rev. 6, available from the NXP website at www.nxp.com.
Page 370 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Serial Communications Block (SCB) • = Total input leakage current of all devices on the bus The supply voltage (V ) limits the minimum pull-up resistor value due to bus devices maximum low output voltage (V ) specifications.
Page 371 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Serial Communications Block (SCB) 26.5.4.2 Bus arbitration The I C protocol is a multi-master, multi-slave interface. Bus arbitration is implemented on master devices by monitoring the SDA line. Bus collisions are detected when the master observes an SDA line value that is not the same as the value it is driving on the SDA line.
Page 372 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Serial Communications Block (SCB) 26.5.5.1 Write transfer • A typical write transfer begins with the master generating a START condition on the I C bus. The master then writes a 7-bit I C slave address and a write indicator (‘0’) after the START condition.
Page 373 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Serial Communications Block (SCB) • If the slave acknowledges the address, it starts transmitting data after the acknowledgment signal. The master transmits an acknowledgment to confirm the receipt of each data byte sent by the slave. Upon receipt of this acknowledgment, the addressed slave may transmit another data byte.
Page 374 26.5.6.2 EZI2C mode The Easy I C (EZI2C) protocol is a unique communication scheme built on top of the I C protocol by Infineon. It uses a meta protocol around the standard I C protocol to communicate to an I C slave using indexed memory transfers.
Page 375 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Serial Communications Block (SCB) EZI2C distinguishes three operation phases: • Address phase: The master transmits an 8-bit address to the slave. This address is used as the slave base and current address. •...
Page 376 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Serial Communications Block (SCB) 26.5.6.3 Command-response mode This mode has a single memory buffer, a base read address, a current read address, a base write address, and a current write address that are used to index the memory buffer. The base addresses are provided by the CPU. The current addresses are used by the slave to index the memory buffer for sequential accesses of the memory buffer.
Page 377 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Serial Communications Block (SCB) 26.5.7 Clocking and oversampling The SCB I C supports both internally and externally clocked operation modes. Two bitfields (EC_AM_MODE and EC_OP MODE) in the SCB_CTRL register determine the SCB clock mode. EC_AM_MODE indicates whether I address matching is internally (0) or externally (1) clocked.
Page 378 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Serial Communications Block (SCB) • If the BLOCK bitfield of SCB_CTRL is ‘0’: An internal logic access to the memory buffer is not blocked, but fails when it conflicts with an external interface logic access. A read access returns the value 0xFFFF:FFFF and a write access is ignored.
Page 379 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Serial Communications Block (SCB) When operating in EC_OP_MODE = 1, the 100-kHz, 400-kHz, and 1000-kHz modes require the following settings for AF_out: AF_in AF_out DF_in 100-kHz mode: I2C_CFG.SDA_OUT_FILT_SEL = 3 400-kHz mode: I2C_CFG.SDA_OUT_FILT_SEL = 3 1000-kHz mode: I2C_CFG.SDA_OUT_FILT_SEL = 1 26.5.7.2 Oversampling and bit rate Internally-clocked master...
Page 380 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Serial Communications Block (SCB) SCL_out SCL_bus SCL_in Figure 26-43. I C SCL turnaround path If the above three delays combined are greater than one clk_scb cycle, then the high phase of the SCL will be extended.
Page 381 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Serial Communications Block (SCB) 26.5.8 Enabling and initializing the I The following section describes the method to configure the I C block for standard (non-EZ) mode and EZI2C mode. 26.5.8.1 Configuring for I C FIFO mode The I C interface must be programmed in the following order.
Page 382 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Serial Communications Block (SCB) 26.5.9 I/O pad connections i2c_ic_block_ec i2c_ctl i2c_ic_scl_out Open drain i2c_ic_sda_out (pull-up) i2c_scl Filter i2c_scl_in i2c_scl_in i2c_sda_in Filter i2c_ec_ctl i2c_ec_scl_out i2c_ec_sda_out i2c_sda Filter i2c_sda_in i2c_scl_in Open drain i2c_sda_in (pull-up) Figure 26-44.
Page 383 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Serial Communications Block (SCB) 26.5.10 C Registers The I C interface is controlled by reading and writing a set of configuration, control, and status registers, as listed Table 26-20. Table 26-20. I C Registers Register Function...
Page 384 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Serial Communications Block (SCB) 26.6 SCB interrupts SCB supports interrupt generation on various events. The interrupts generated by the SCB block vary depending on the mode of operation. Table 26-21. SCB interrupts Interrupt Functionality Active/Deep...
Page 385 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Serial Communications Block (SCB) Note: While registers corresponding to INTR_M are used here, these definitions can be used for INTR_S, INTR_TX, INTR_RX, INTR_I2C_EC, and INTR_SPI_EC. Figure 26-45 shows the physical interrupt lines. All the interrupts are OR'd together to make one interrupt source that is the OR of all six individual interrupts.
Page 386 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Serial Communications Block (SCB) – TX FIFO overflow – Firmware attempts to write to a full TX FIFO. – TX FIFO underflow – Hardware attempts to read from an empty TX FIFO. This happens when the SCB is ready to transfer data and EMPTY is ‘1’.
Page 387 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Serial Communications Block (SCB) Component Started Write 1 byte Write 1 more byte Write 4 more bytes Write 3 more bytes TX FIF O Empty TX FIF O Empty TX FIF O Empty TX FIF O Empty = 0 (W1C) TX FIF O Empty...
Page 388 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Serial Communications Block (SCB) Component Started Recevice 1 byte Receive 4 more byte Receive 3 more bytes Receive 3 more bytes RX FIFO N ot Empty = 1 RX FIFO N ot Empty = 0 RX FIFO N ot Empty = 1 RX FIFO N ot Empty = 1 RX FIFO N ot Empty = 1...
Page 389 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Serial Communications Block (SCB) – TX NACK – UART transmitter receives a negative acknowledgment in SmartCard mode. – TX done – This happens when the UART completes transferring all data in the TX FIFO and the last stop field is transmitted (both TX FIFO and transmit shifter register are empty).
Page 390 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Serial Communications Block (SCB) Component Started Write 1 byte Write 1 more byte Write 4 more bytes Write 3 more bytes TX FIF O Empty TX FIF O Empty TX FIF O Empty TX FIF O Empty = 0 (W1C) TX FIF O Empty...
Page 391 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Serial Communications Block (SCB) Component Started Recevice 1 byte Receive 4 more byte Receive 3 more bytes Receive 3 more bytes RX FIFO N ot Empty = 1 RX FIFO N ot Empty = 0 RX FIFO N ot Empty = 1 RX FIFO N ot Empty = 1 RX FIFO N ot Empty = 1...
Page 392 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Serial Communications Block (SCB) 26.6.3 C interrupts C interrupts can be classified as master interrupts, slave interrupts, TX interrupts, RX interrupts, and externally clocked (EC) mode interrupts. Each interrupt output is the logical OR of the group of all possible interrupt sources classified under the section.
Page 393 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Serial Communications Block (SCB) – TX FIFO underflow – Hardware attempts to read from an empty TX FIFO. • C RX – RX FIFO has more entries than the value specified by TRIGGER_LEVEL in SCB_RX_FIFO_CTRL. –...
Page 394 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Serial memory interface (SMIF) Serial memory interface (SMIF) This PSoC™ 6 MCU reference manual provides comprehensive and detailed information about the functions of the PSoC™ 6 MCU device hardware. It is divided into two books: architecture reference manual and registers reference manual.
Page 395 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Serial memory interface (SMIF) memory. The typical use case for the XIP mode is to execute code placed in external memory. Thus executing code from external memory is seamless. SMIF MMIO AHB-Lite AHB-Lite AHB-Lite interface...
Page 396 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Serial memory interface (SMIF) implement any memory device transfer. For example, memory device transfers to setup, program, or erase the external memory devices. In an XIP AHB-Lite interface, access is supported through XIP: AHB-Lite read and write transfers are automatically (by the hardware) translated in memory device read and write transfers.
Page 397 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Serial memory interface (SMIF) Together, the four command types can be used to construct any SPI transfer. The Tx command FIFO is used by both the memory interface transmit and receive logic. This ensures lockstep operation. The Tx command is a representation of a queue of commands that are to be processed.
Page 398 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Serial memory interface (SMIF) 27.2.2 Command mode If CTL.XIP_MODE is ‘0’, the SMIF is in Command mode. Software generates SPI transfers by accessing the Tx FIFOs and Rx FIFO. Software writes to the Tx FIFOs and reads from the Rx FIFO. The Tx command FIFO has formatted commands (Tx, TX_COUNT, RX_COUNT, and DUMMY_COUNT) that are described in the registers reference manual.
Page 399 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Serial memory interface (SMIF) • The SMIF is not in XIP_MODE (SMIFn_CTL.XIP_MODE is ‘0’). • The transfer request is not in a memory region. • The transfer is a write and the identified memory region does not support writes (SMIFn_DEVICEn_CTL.WR_EN is ‘0’).
Page 400 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Serial memory interface (SMIF) 27.2.7 Cryptography In XIP mode, a cryptography component supports on-the-fly encryption for write data and on-the-fly decryption for read data. The use of on-the-fly cryptography is determined by a device’s MMIO CTL.CRYPTO_EN field. In Command mode, the cryptography component is accessible through a register interface to support offline encryption and decryption.
Page 401 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Serial memory interface (SMIF) encrypted read data encrypted write data ciphertext CT[127:0] {CRYPTO_KEY3, AES-128 forward CRYPTO_KEY2, block cipher CRYPTO_KEY1, CRYPTO_KEY0} decrypted read data decrypted write data {CRYPTO_INPUT3, CRYPTO_INPUT2, CRYPTO_INPUT1, A[31:4], CRYPT0_INPUT0.INPUT[3:0]} Figure 27-3.
Page 402 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Serial memory interface (SMIF) In dual quad SPI mode, each memory device contributes a 4-bit nibble for each 8-bit byte. However, both memory devices are quad SPI memories with a byte interface. Therefore, the transfer size must be a multiple of 2. The XIP_ALIGNMENT_ERROR interrupt cause is set under the following conditions (in XIP mode and when ADDR_CTL.DIV2 is ‘1’): •...
Page 403 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Serial memory interface (SMIF) • Use shared data signal connections. • Use dedicated data signal connections. This reduces the load on the data lines allowing faster signal level changes, which in turn allows for a faster I/O interface. Note that dual-quad SPI mode requires dedicated data signals to enable read and/or write data transfer from and to two quad SPI devices simultaneously.
Page 404 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Serial memory interface (SMIF) Figure 27-6 illustrates memory devices 0 and 1, both of which are single SPI memories. Each device uses dedicated data signal connections. The device address regions in the PSoC™ 6 MCU address space must be non- overlapping to ensure that the activation of select[0] and select[1] are mutually exclusive.
Page 405 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Serial memory interface (SMIF) CTL.DATA_SEL[1:0] = 0 Device 0: Quad SPI spi_clk memory SMIF spi_select[0] SI/IO0 SO/IO1 WP/IO2 HOLD/IO3 spi_data[0] spi_data[1] spi_data[2] spi_data[3] Figure 27-8. Quad SPI memory device 0 Figure 27-9 illustrates memory devices 0 and 1, device 0 is a single SPI memory and device 1 is a quad SPI memory.
Page 406 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Serial memory interface (SMIF) CTL.DATA_SEL[1:0] = 0 Device 0: SPI memory spi_clk SMIF spi_select[0] spi_select[1] CTL.DATA_SEL[1:0] = 0 Device 1: Quad SPI spi_data[0] memory spi_data[1] spi_data[2] SI/IO0 spi_data[3] SO/IO1 WP/IO2 HOLD/IO3 Figure 27-10.
Page 407 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Serial memory interface (SMIF) CTL.DATA_SEL[1:0] = 0 Device 0: Octal SPI spi_clk memory SMIF spi_select[0] spi_data[0] spi_data[1] spi_data[2] spi_data[3] spi_data[4] spi_data[5] spi_data[6] spi_data[7] Figure 27-12. Octal SPI memory device 0 27.3.3 SPI data transfer SPI data transfer uses most-significant-bit (MSb) for the first data transfer.
Page 408 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Serial memory interface (SMIF) For a dual SPI device and device data signal connections to data[1:0] (DATA_SEL is “0”), Table 27-4 summarizes the transfer of byte B. Table 27-4. Dual data transfer Cycle Data transfer b7, b6 are transferred on data[1:0] and IO1, IO0.
Page 409 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Serial memory interface (SMIF) 27.3.4 Example of setting up SMIF Devices 0 and 1 are used to implement the dual-quad SPI mode. Both devices are 1 MB / 8 Mb; the address requires 3 bytes.
Page 410 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Serial memory interface (SMIF) 0xEB instruction, instruction 1 bit/cycle; address, mode, data 4 bits/cycle spi_select[0] spi_select[1] spi_clk 4 dummy 24 bit address instruction (0xeb) 8-bit data mode cycles spi_data[0] spi_data[1] spi_data[2] spi_data[3] spi_data[4] spi_data[5]...
Page 411 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Serial memory interface (SMIF) • The MMIO RX_DATA_FIFO_CTL.TRIGGER_LEVEL field specifies a number of FIFO entries. The tr_rx_req trigger is active when the number of used Rx data FIFO entries is greater than the specified number; that is, RX_DATA_FIFO_STATUS.USED >...
Page 412 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Timer, Counter, and PWM (TCPWM) Timer, Counter, and PWM (TCPWM) This PSoC™ 6 MCU reference manual provides comprehensive and detailed information about the functions of the PSoC™ 6 MCU device hardware. It is divided into two books: architecture reference manual and registers reference manual.
Page 413 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Timer, Counter, and PWM (TCPWM) 28.2 Architecture Co unter i T rigger inp uts Event Configuration 16-b it or 32-b it co unter G eneratio n registers p w m , cou nter_en interrup t und erflow ,...
Page 414 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Timer, Counter, and PWM (TCPWM) 28.2.2 Clocking Each TCPWM counter can have its own clock source and the only source for the clock is from the configurable peripheral clock dividers generated by the clocking system; see the “Clocking system”...
Page 415 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Timer, Counter, and PWM (TCPWM) • Stop/kill • Count • Capture/swap When starting a TCPWM for the first time it is recommended that a reload is used, because a reload will generate an overflow or underflow on startup.
Page 416 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Timer, Counter, and PWM (TCPWM) MODE = CAPTURE UP_DOWN_MODE = COUNT_UP Even number of capture Odd number of capture CAPTURE_EDGE = BOTH_EDGES events => single capture events => no capture reload capture CC_BUFF PERIOD = 4...
Page 417 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Timer, Counter, and PWM (TCPWM) 28.2.5 Interrupts The TCPWM block provides a dedicated interrupt output for each counter. This interrupt can be generated for a terminal count (TC) or CC event. A TC is the logical OR of the OV and UN events. Four registers are used to handle interrupts in this block, as shown in Table 28-1.
Page 418 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Timer, Counter, and PWM (TCPWM) 28.2.7 Power modes The TCPWM block works in Active and Sleep modes. The TCPWM block is powered from V . The configuration registers and other logic are powered in Deep Sleep mode to keep the states of configuration registers. See Table 28-3 for details.
Page 419 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Timer, Counter, and PWM (TCPWM) Table 28-5. Counting mode configuration Counting modes UP_DOWN_M Description ODE[17:16] UP Counting Mode Increments the counter until the period value is reached. A Terminal Count (TC) and Overflow (OV) condition is generated when the counter changes from the period value.
Page 420 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Timer, Counter, and PWM (TCPWM) Table 28-6. Timer mode trigger input description (continued) Trigger inputs Usage Count Count event increments/decrements the counter. Capture Not used. Incrementing and decrementing the counter is controlled by the count event and the counter clock clk_counter. Typical operation will use a constant ‘1’...
Page 421 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Timer, Counter, and PWM (TCPWM) Table 28-10. Timer mode PWM outputs PWM outputs Description Not used. pwm_n Not used. Timer Interrupt interrupt generation Reload PERIOD Start cc_match tr_cc_match Stop Trigger underflow tr_underflow Count generation...
Page 422 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Timer, Counter, and PWM (TCPWM) Figure 28-8 illustrates a timer in “one-shot” operation mode. Note that the counter is stopped on a tc event. MODE = TIMER UP_DOWN_MODE = COUNT_UP ONE_SHOT = 1 reload PERIOD = 4 CC = 2...
Page 423 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Timer, Counter, and PWM (TCPWM) Figure 28-11 illustrates a timer that uses both CC and CC_BUFF registers. Note that CC and CC_BUFF are exchanged on a cc_match event. MODE = TIMER UP_DOWN_MODE = COUNT_UP AUTO_RELOAD_CC = 1 CC_BUFF...
Page 424 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Timer, Counter, and PWM (TCPWM) MODE = TIMER UP_DOWN_MODE = COUNT_UPDN1 COUNTER starts with 1 period is 2*PERIOD reload PERIOD = 4 CC = 2 Underflow (UN) Overflow (OV) Terminal Count (TC) Compare/Capture (CC) no TC event CC event on leaving the...
Page 425 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Timer, Counter, and PWM (TCPWM) MODE = TIMER UP_DOWN_MODE = COUNT_UPDN2 COUNTER starts with 1 period is 2*PERIOD reload PERIOD = 4 CC = 2 Underflow (UN) Overflow (OV) Terminal Count (TC) Compare/Capture (CC) no TC event CC event on leaving the...
Page 426 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Timer, Counter, and PWM (TCPWM) 28.3.2 Capture mode The capture functionality increments and decrements a counter between 0 and PERIOD. When the capture event is activated the counter value COUNTER is copied to CC (and CC is copied to CC_BUFF). The capture functionality can be used to measure the width of a pulse (connected as one of the input triggers and used as capture event).
Page 427 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Timer, Counter, and PWM (TCPWM) Table 28-14. Capture mode interrupt outputs Interrupt outputs Description Specified by UP_DOWN_MODE: • COUNT_UP: tc event is the same as the overflow event. • COUNT_DOWN: tc event is the same as the underflow event. •...
Page 428 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Timer, Counter, and PWM (TCPWM) MODE = CAPTURE UP_DOWN_MODE = COUNT_UP CAPTURE_EDGE = RISING_EDGE reload capture CC_BUFF PERIOD = 4 Underflow (UN) Overflow (OV) Terminal Count (TC) Compare/Capture (CC) Figure 28-17. Capture in up counting mode When multiple capture events are detected before the next “active count”...
Page 429 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Timer, Counter, and PWM (TCPWM) 8. Set the TCPWM_CNT_TR_CTRL1 register to select the edge that causes the event (reload, start, stop, capture, and count). 9. If required, set the interrupt upon TC or CC condition. 10.
Page 430 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Timer, Counter, and PWM (TCPWM) Table 28-19. Quadrature mode interrupt outputs Interrupt outputs Description cc_match (CC) Counter value COUNTER equals 0 or 0xFFFF or 0xFFFFFFFF (32-bit mode) or a reload/index event. Reload/index event.
Page 431 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Timer, Counter, and PWM (TCPWM) Note that a counter increment/decrement can coincide with a reload/index/tc event or with a situation cc_match event. Under these circumstances, the counter value set to either 0x8000+1 or 0x80000000+1 (increment) or 0x8000–1 or 0x80000000–1 (decrement).
Page 432 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Timer, Counter, and PWM (TCPWM) Quadrature decoding counter cycle decrement behavior, no coinciding underflow with decr1 event underflow without decr1 event reload and decrement events Reload / Index incr1 decr1 COUNTER 0x8000 0x7FFFF 0x7ffe...
Page 433 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Timer, Counter, and PWM (TCPWM) 28.3.3.1 Configuring counter for Quadrature mode The steps to configure the counter for quadrature mode of operation and the affected register bits are as follows. 1. Disable the counter by writing ‘1’ to the TCPWM_CTRL_CLR register. 2.
Page 434 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Timer, Counter, and PWM (TCPWM) Table 28-22. PWM mode supported features Supported features Description Clock pre-scaling Pre-scales the counter clock “clk_counter”. One-shot Counter is stopped by hardware, after a single period of the counter: •...
Page 435 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Timer, Counter, and PWM (TCPWM) Table 28-24. PWM mode interrupt output description Interrupt outputs Description Specified by UP_DOWN_MODE: • COUNT_UP: tc event is the same as the overflow event. • COUNT_DOWN: tc event is the same as the underflow event. •...
Page 436 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Timer, Counter, and PWM (TCPWM) pwm polarity underflow Dead time kill period pwm_dt_input overflow generation insertion cc_match pwm_n pwm_n polarity only supported in TCPWM_CNT_TR_CTRL2 PWM_DT mode Figure 28-24. PWM output generation PWM polarity and PWM_n polarity as seen in Figure 28-24, allow the PWM outputs to be inverted.
Page 437 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Timer, Counter, and PWM (TCPWM) MODE = PWM UP_DOWN_MODE = COUNT_UP reload PERIOD = 4 Underflow (UN) Overflow (OV) Terminal Count (TC) Compare/Capture (CC) Left aligned PWM CC = pulse width OVERFLOW_MODE = SET CC_MATCH_MODE = CLEAR Right aligned PWM...
Page 438 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Timer, Counter, and PWM (TCPWM) MODE = PWM UP_DOWN_MODE = COUNT_DOWN reload -1 / 0xFFFF PERIOD = 4 Underflow (UN) Overflow (OV) Terminal Count (TC) Compare/Capture (CC) Right aligned PWM CC = pulse width - 1 UNDERFLOW_MODE = CLEAR CC_MATCH_MODE = SET Left aligned PWM...
Page 439 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Timer, Counter, and PWM (TCPWM) Note: • The actual counter value COUNTER from before the reload event is NOT used. Instead the counter value before the reload event is considered to be 0. As a result, when the first CC value at the reload event is 0, a cc_match event is generated.
Page 440 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Timer, Counter, and PWM (TCPWM) Right aligned PWM PWM_STOP_ON_KILL = 1 pwm and pwm_n set to programmed kill event stops counter STOP_EDGE = RISING_EDGE polarity pwm polarity = 0, pwm_n polarity = 0 cc_match pwm_dt_input kill...
Page 441 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Timer, Counter, and PWM (TCPWM) MODE = PWM UP_DOWN_MODE = COUNT_UPDN1 SW update SW update CC_BUFF PERIOD_BUFF reload PERIOD Underflow (UN) Overflow (OV) Terminal Count (TC) Compare/Capture (CC) upcounting and CC = 0 => cc_matchŏ...
Page 442 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Timer, Counter, and PWM (TCPWM) Right aligned PWM PWM_STOP_ON_KILL = 0, PWM_SYNC_KILL = 0 STOP_EDGE = NO_EDGE_DET pwm polarity = 0, pwm_n polarity = 0 cc_match pwm_dt_input kill pwm_n Figure 28-35. PWM outputs when killed 28.3.4.1 Asymmetric PWM This PWM mode supports the generation of an asymmetric PWM.
Page 443 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Timer, Counter, and PWM (TCPWM) MODE = PWM UP_DOWN_MODE = COUNT_UPDN2 CC_BUFF reload PERIOD = 4 Underflow (UN) Overflow (OV) Terminal Count (TC) Compare/Capture (CC) Asymmetric PWM CC = PERIOD – pulse width/2 UNDERFLOW_MODE = CLEAR OVERFLOW_MODE = SET CC_MATCH_MODE = INVERT...
Page 444 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Timer, Counter, and PWM (TCPWM) 28.3.4.2 Configuring counter for PWM mode The steps to configure the counter for the PWM mode of operation and the affected register bits are as follows. 1.
Page 445 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Timer, Counter, and PWM (TCPWM) Figure 28-39 illustrates dead time insertion for different dead times and different output signal polarity settings. pwm_dt_input MODE = PWM_DT dead time = 0 pwm polarity = 0 pwm_n polarity = 0 pwm_n MODE = PWM_DT...
Page 446 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Timer, Counter, and PWM (TCPWM) 28.3.5.1 Configuring counter for PWM with Dead Time mode The steps to configure the counter for PWM with Dead Time mode of operation and the affected register bits are as follows: 1.
Page 447 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Timer, Counter, and PWM (TCPWM) Note: Event detection is on the peripheral clock, clk_peri. Table 28-27. PWM_PR supported features Supported features Description Clock pre-scaling Pre-scales the counter clock, clk_counter. One-shot Counter is stopped by hardware, after a single period of the counter (counter value equals period value PERIOD).
Page 448 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Timer, Counter, and PWM (TCPWM) The PWM_PR functionality is described as follows: • The counter value COUNTER is initialized by software (to a value different from 0). • A reload or start event starts PWM_PR operation. •...
Page 449 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Timer, Counter, and PWM (TCPWM) MODE = PWM_PR COUNTER is exactly 0xe771 reload 0xFFFF PERIOD = 0xe771 CC = 0x4000 cc_match pwm_dt_input Only the lower 15 bits of the counter value are used. Figure 28-42.
Page 450 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Timer, Counter, and PWM (TCPWM) 28.4 TCPWM registers Table 28-31. List of TCPWM registers Register Comment Features TCPWM_CTRL TCPWM control register Enables the counter block TCPWM_CTRL_CLR TCPWM control clear register Used to avoid race-conditions on read- modify-write attempt to the CTRL register TCPWM_CTRL_SET TCPWM control set register...
Page 451 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Timer, Counter, and PWM (TCPWM) Table 28-31. List of TCPWM registers (continued) Register Comment Features TCPWM_CNT_INTR_MASK Interrupt mask register Mask for interrupt request register TCPWM_CNT_INTR_MASKED Interrupt masked request register Bitwise AND of interrupt request and mask registers Reference manual 002-18176 Rev.
Page 452 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Inter-IC Sound Bus Inter-IC Sound Bus This PSoC™ 6 MCU reference manual provides comprehensive and detailed information about the functions of the PSoC™ 6 MCU device hardware. It is divided into two books: architecture reference manual and registers reference manual.
Page 453 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Inter-IC Sound Bus Figure 29-1 shows the high-level block diagram of the I S block, which consists of two sub-blocks – I Transmitter (Tx) and I S Receiver (Rx). The digital audio interface format and master/slave mode configuration can be done independently for the Tx and Rx blocks.
Page 454 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Inter-IC Sound Bus (1) Channel Length = 32-bits Left Channel Right Channel (Channel Length = 32-bit) (Channel Length = 32-bit) Word Length = 32-bit mode Word Length = 24-bit mode Word Length = 20-bit mode Word Length = 18-bit mode Word Length = 16-bit mode Word Length = 8-bit mode...
Page 455 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Inter-IC Sound Bus Table 29-1. Word length and channel length combinations Word length 8-bit 16-bit 18-bit 20-bit 24-bit 32-bit Channel 32-bit Valid Valid Valid Valid Valid Valid Length 24-bit Valid Valid Valid Valid Valid...
Page 456 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Inter-IC Sound Bus equal to eight channels. The unused (inactive) channels always follow the active channels in a frame. As an example, if CH_NR is set for four channels, CH0 to CH3 are the active channels and CH4 to CH7 are the unused channels.
Page 457 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Inter-IC Sound Bus in the I2S_RX_CTL register is set. This feature can be used if there are timing issues while operating the I S Rx block in master mode. In addition to these clock delay options, there is also an option to invert the outgoing bit clock (sck) in master mode by setting the SCKO_POL bit in the I2S_TX_CTL and I2S_RX_CTL registers.
Page 458 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Inter-IC Sound Bus 29.6 Clocking features The I S unit has three clock inputs. Table 29-2. Clock inputs Signal Description clk_sys_i2s System clock. This clock is used for the AHB slave Interface, control, status, and interrupt registers, and also clocks the DMA trigger control logic.
Page 459 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Inter-IC Sound Bus Table 29-3. I S Divider values for standard audio sampling rates in standard I S format Sampling WORD_LEN CLK_HF1 (CLK_HF[1])/S CLK_CLOCK_D Second stage rate (SR) (bits) (2*WORD_LEN* CK (Total IV (First divider (kHz)
Page 460 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Inter-IC Sound Bus For Tx FIFO data writes using the CPU, the hardware can be used to trigger an interrupt event for any of the FIFO conditions such as TX_TRIGGER, TX_NOT_FULL, and TX_EMPTY. As part of the interrupt handler, the CPU can write to the I2S_TX_FIFO_WR register.
Page 461 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Inter-IC Sound Bus The I S Rx FIFO write pointer is updated whenever the data is transferred to the Rx FIFO from the internal receive buffer. Rx FIFO read pointer is updated whenever the data is read from the I2S_RX_FIFO_RD register, either through the CPU or the DMA controller.
Page 462 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Inter-IC Sound Bus 29.8 Interrupt support The I S block has one interrupt output signal that goes to the interrupt controller in the CPU. Refer to the “Interrupts” on page 57 for details on the vector number of the I S interrupt and the procedure to configure the interrupt priority, vector address, and enabling/disabling.
Page 463 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Inter-IC Sound Bus tx_ws (input to PSoC™ 6 MCU) (or rx_ws) Reloads watchdog timer Reloads watchdog timer when watchdog timer for tx on rising edge of tx_ws (or timer value is 0. Interrupt (or rx) rx_ws) event generated...
Page 464 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture PDM-PCM converter PDM-PCM converter This PSoC™ 6 MCU reference manual provides comprehensive and detailed information about the functions of the PSoC™ 6 MCU device hardware. It is divided into two books: architecture reference manual and registers reference manual.
Page 465 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture PDM-PCM converter 30.2.1 Enable/disable converter The PDM-PCM converter can be powered ON or OFF by using the ENABLED bit in the PDM_CTL register. The block can be turned OFF when not used to save power. When the block is powered off by writing ‘0’ to the ENABLED bit, the non-retention registers lose their current values.
Page 466 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture PDM-PCM converter See the device datasheet for details on maximum values of PDM_CKO frequency, PDM_CLK frequency, and the output sampling rates. Table 30-1. PDM clock divider values for standard audio sampling rates Sampli SINC_RAT PDM_CKO...
Page 467 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture PDM-PCM converter Table 30-2. Operation Mode Register settings (continued) Register setting Operation mode PCM_CH_SET = 3, SWAP_LR = 1 Swapped Stereo recording mode. The right microphone channel is sampled on the rising edge of PDM_CKO and left channel on falling edge.
Page 468 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture PDM-PCM converter 30.2.5 Hardware FIFO buffers and DMA controller support The PDM-PCM converter has a hardware FIFO depth of 255 elements where each element is 24-bit wide. The PDM_RX_FIFO_CTL register is used for FIFO control operations. Refer to the register description in the registers reference manual for more details.
Page 469 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture PDM-PCM converter read data format of PDM_RX_FIFO 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 WORD_LEN = 24-bit mode fixed "0"...
Page 470 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture PDM-PCM converter PDM_INTR_MASKED.RX_TRIGGER (Register bit) PDM_INTR.RX_TRIGGER RX_TRIGGER (Register bit) (Hardware event signal) interrupt_pdm PDM_INTR_MASK.RX_TRIGGER (To interrupt controller) PDM_INTR_SET.RX_TRIGGER (Register bit) (Register bit, Software triggered event) Other interrupt Trigger events (RX_OVERFLOW etc) (PDM_INTR &...
Page 471 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture PDM-PCM converter When mute function is disabled by setting SOFT_MUTE = 0, the mute function is OFF and the PDM-PCM returns to normal operation where output signal level goes up to normal with current PGA gain. 30.2.10 Word length and sign bit extension The PCM output word length can be configured for either 16-bits, 18-bits, 20-bits, or 24-bits using WORD_LEN bits...
Page 472 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture PDM-PCM converter 3. Configure the PDM_MODE_CTL and PDM_DATA_CTL registers as required. 4. Configure the Rx FIFO trigger level setting by writing to the TRIGGER_LEVEL bits in the PDM_RX_FIFO_CTL register. The CLEAR and FREEZE bits in PDM_RX_FIFO_CTL are not set for normal operation. 5.
Page 473 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Universal Serial Bus (USB) device mode Universal Serial Bus (USB) device mode This PSoC™ 6 MCU reference manual provides comprehensive and detailed information about the functions of the PSoC™ 6 MCU device hardware. It is divided into two books: architecture reference manual and registers reference manual.
Page 474 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Universal Serial Bus (USB) device mode 31.2 Architecture Figure 31-1 illustrates the device architecture of the USB block in PSoC™ 6 MCUs. It consists of the USB Physical Layer (USB PHY), Serial Interface Engine (SIE), and the local 512-byte memory buffer. USB Block Arbiter CPU/DMA...
Page 475 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Universal Serial Bus (USB) device mode 31.2.3 Arbiter The Arbiter handles access of the SRAM memory by the endpoints. The SRAM memory can be accessed by the CPU, DMA, or SIE. The arbiter handles the arbitration between the CPU, DMA, and SIE. The arbiter consists of the following blocks: •...
Page 476 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Universal Serial Bus (USB) device mode • Use external clock (EXTCLK) with the required accuracy 31.3.2 USB PHY The USB includes the transmitter and receiver (transceiver), which corresponds to the USB PHY. Figure 31-2 shows the PHY architecture.
Page 477 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Universal Serial Bus (USB) device mode 31.3.2.3 USB D+ pin pull-up enable logic When a USB device is self-powered, the USB specification warrants that the device enable the pull-up resistor on its D+ pin to identify itself as a full-speed device to the host.
Page 478 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Universal Serial Bus (USB) device mode 31.3.4 Transfer types The PSoC™ 6 MCU USB supports full-speed transfers and is compliant with the USB 2.0 specification. It supports four types of transfers: •...
Page 479 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Universal Serial Bus (USB) device mode 31.3.5.3 Data endpoint interrupt events These are eight interrupt events corresponding to each data endpoint (EP1-EP8). Each of the endpoint interrupt events can be enabled/disabled by using the corresponding bit in the USBDEV_SIE_EP_INT_EN register. The interrupt status of each endpoint can be known by reading the USBDEV_SIE_EP_INT_SR status register.
Page 480 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Universal Serial Bus (USB) device mode 31.3.5.7 Arbiter interrupt event The arbiter interrupt can arise from five possible sources. Each interrupt source is logically ANDed with its corresponding ENABLE bit and the results are logically ORed to result in a single arbiter interrupt event. The arbiter interrupt event can arise under any of the following five scenarios: •...
Page 481 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Universal Serial Bus (USB) device mode either the DMA transfer descriptor transfer size or the USBDEV_DMA_THRESH and USBDEV_DMA_THRESH_MSB registers. – In an OUT endpoint, the common area overflow occurs when the data written to the common area has not yet been read and new data overwrites the existing data.
Page 482 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Universal Serial Bus (USB) device mode Table 31-1 gives a comparison of the two transfer modes. Table 31-1. USB transfer modes Feature Store and Forward mode Cut Through mode SRAM Memory Requires more memory Requires less memory Usage...
Page 483 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Universal Serial Bus (USB) device mode Table 31-2. Endpoint registers (continued) Register Comment Content Usage USBDEV_ARB_RWx_DR Endpoint Data 8-Bit Data Data register is read/written to perform any Register transaction. IN command: Data written to the data register is copied to the SRAM location specified by the WA register.
Page 484 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Universal Serial Bus (USB) device mode 31.4.1 Manual memory management with no DMA access All operations in this mode are controlled by the CPU and works in a store-and-forward operation mode. An entire packet is transferred to the memory and a mode bit (such as ACK IN or ACK OUT) is set by the CPU.
Page 485 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Universal Serial Bus (USB) device mode Set Base address to WA Set Packet size in the Endpoint byte count register Set mode in CR0 register Wait Is OUT Responds automatically Token Received? with ACK Data received from host Written to SRAM location WA...
Page 486 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Universal Serial Bus (USB) device mode Write WA register (based on required memory allocation) Set Packet size in the Endpoint byte count register Set the DMA request in USBDEV_ARB_EPx_CFG register Value automatically written to the SRAM specified by WA DMA writes data to Endpoint Data Register WA++...
Page 487 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Universal Serial Bus (USB) device mode Write WA register (based on the required memory allocation) Set Packet size in the Endpoint byte count register Set mode in CR0 register Wait Is OUT Responds automatically with ACK Token Received? Data received from host...
Page 488 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Universal Serial Bus (USB) device mode 31.4.3 Automatic DMA mode This is the Automatic memory management mode with auto DMA access. The CPU programs the initial buffer size requirement for IN/OUT packets and informs the arbiter block of the endpoint configuration details for the particular application.
Page 489 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Universal Serial Bus (USB) device mode Set Packet size in the Endpoint byte count register Set IN_DATA_RDY for the endpoint in ARB_EP1_CFG register This memory location is very limited. The memory location is filled initially to make sure Block automatically raises interrupt the host does not stall when an IN command is for DMA...
Page 490 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Universal Serial Bus (USB) device mode Write maximum bytes to Byte Count register Program the Mode register for the endpoint Wait Is OUT Token Received? The DMA writes the received data to the SRAM in location specified by WA WA++ Is data in...
Page 491 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Universal Serial Bus (USB) device mode Set the mode bits to ACK the IN token Is SETUP token received? The block ACKs it Generates Interrupt and sets the bit in EP0_CR register to indicate that SETUP token was received Read the status bit and data valid Is Data Valid?
Page 492 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Universal Serial Bus (USB) device mode Program the mode bits for ACK_OUT Is SETUP token received? The block ACKs it Generates Interrupt and sets the bit in EP0_CR register to indicate that SETUP token was received Read the data valid bit in EP0_CNT Is Data Valid? Read the EP0_DRx register to find the type of...
Page 493 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Universal Serial Bus (USB) device mode 31.5 USB power modes The USB supports two modes of operation: • Active mode: In this mode, the USB is powered up and clocks are turned on. •...
Page 494 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Universal Serial Bus (USB) device mode Table 31-3. USB registers (continued) Name Description USBDEV_EP_TYPE Endpoint type (IN/OUT) indication register USBDEV_ARB_EPx_CFG Endpoint configuration register USBDEV_ARB_EPx_INT_EN Endpoint interrupt enable register USBDEV_ARB_EPx_SR Endpoint interrupt enable register USBDEV_ARB_CFG Arbiter configuration register USBDEV_USB_CLK_EN...
Page 495 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Universal Serial Bus (USB) host Universal Serial Bus (USB) host This PSoC™ 6 MCU reference manual provides comprehensive and detailed information about the functions of the PSoC™ 6 MCU device hardware. It is divided into two books: architecture reference manual and registers reference manual.
Page 496 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Universal Serial Bus (USB) host 32.2 Architecture Interrupt Interrupt Control / Status Registers Control Signals Block Endpoint Block Endpoint 1 VDDUSB Host USB Clock Clock (48 MHz) Controller Control Block FIFO Control Unit System Clock (at least 13 MHz)
Page 497 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Universal Serial Bus (USB) host 32.2.4 Endpoint n (n=1, 2) The USB host has two endpoints. The maximum buffer size of endpoint 1 is 256 bytes and that of endpoint 2 is 64 bytes.
Page 498 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Universal Serial Bus (USB) host • If TMODE=1, then the device is a full-speed device • If TMODE=0, then the device is a low-speed device Figure 32-3 shows the flow chart for device connection detection and obtaining the transfer speed. START Enable pull down resistors on D+ and D - POWER_CTL.DP_DOWN_EN=1...
Page 499 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Universal Serial Bus (USB) host Pin D+ 10 ms or more Pin D- URST bit of USBHOST_HOST_STATUS CSTAT bit of USBHOST_HOST_STATUS URIRQ bit of USBHOST_INTR_USBHOST CNNIRQ bit of USBHOST_INTR_USBHOST 2.5 µs or more Write ‘1’...
Page 500 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Universal Serial Bus (USB) host 8. Check for token packet transfer errors using the USBHOST_HOST_ERR register. Handle the errors, if any, appropriately. 9. Read the EPnDRQ (n = 1 or 2) bit of the USBHOST_INTR_HOST_EP register. A value of ‘1’ indicates that the packet transfer ended normally.
Page 501 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Universal Serial Bus (USB) host START Set the BFINI bit of HOST_EP1_CTL and HOST_EP2_CTL to ‘1' Set DIR bit HOST_EP1_CTL and HOST_EP2_CTL to ‘1’ or ‘0’. Set the BFINI bit of HOST_EP1_CTL and HOST_EP2_CTL to ‘0' Specify the target address in HOST_ADDR Configure the packet size for the endpoints using the...
Page 502 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Universal Serial Bus (USB) host START Set the BFINI bit of HOST_EP1_CTL and HOST_EP2_CTL to ‘1' Set DIR bit HOST_EP1_CTL and HOST_EP2_CTL to ‘1’ or ‘0’. Set the BFINI bit of HOST_EP1_CTL and HOST_EP2_CTL to ‘0' Specify the target address in HOST_ADDR Configure the packet size for the endpoints using the...
Page 503 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Universal Serial Bus (USB) host An SOF is automatically sent every 1 ms while the SOFBUSY bit of the USBHOST_HOST_STATUS register is ‘1’. Figure 32-7 depicts steps to send an SOF token. START HOST_FRAME Setting HOST_EOF Setting...
Page 504 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Universal Serial Bus (USB) host 32.3.4.2 Data packet Follow these steps to send or receive a data packet after sending a token packet. • Transmitting data (host to device) – Sync pattern is automatically sent. –...
Page 505 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Universal Serial Bus (USB) host 32.3.6 Error status The USB host supports detection of the following types of errors: • Stuffing error If 1 is writer to six successive bits, 0 is inserted into one bit. If 1 is successively detected in seven bits, it is regarded as a Stuffing error, and the STUFF bit of the USBHOST_HOST_ERR register is set to 1.
Page 506 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Universal Serial Bus (USB) host Write data to the TKNEN bit of HTOKEN. J-ST Sync FRAME CRC5 J-ST CMPIRQ bit (HIRQ) J-ST : J State : Token FRAME : Frame Number Figure 32-10.
Page 507 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Universal Serial Bus (USB) host • Device connection and disconnection events The CNNIRQ bit of the USBHOST_INTR_USBHOST register is set to ‘1’ when a device connection is detected. The interrupt can be enabled by setting the CNNIRQM bit of the USBHOST_INTR_USBHOST_MASK register. When a device is disconnected, an interrupt is generated if the DIRQM bitfield of USBHOST_INTR_USBHOST_MASK is set to ‘1’.
Page 508 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Universal Serial Bus (USB) host 32.3.9.1 Packet transfer mode The packet transfer mode transfers each packet according to the configured data size in DMA. This transfer mode can access each buffer of the endpoints. In the packet transfer mode the OUT direction transfer (host to device) involves the following sequence of steps: 1.
Page 509 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Universal Serial Bus (USB) host 1. After the EPnDRQ bit (n=1 or 2) of the USBHOST_INTR_HOST_EP register is set and the interrupt handling is entered, check the transfer data size. 2. Configure the DMA register setting relevant to the number of transfers and block size corresponding to the transfer data size, and then enable DMA to start the transfer.
Page 510 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Universal Serial Bus (USB) host 0x22 0x11 (byte 2) (byte 1) 0x33 0x44 (byte 3) (byte 4) DMA Transfer (Write) 0x66 0x55 (byte 6) (byte 5) 0x77 0x88 (byte 7) (byte 8) Write the data to the 0x99 HOST_Epn_RW1_DR by software...
Page 511 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Universal Serial Bus (USB) host Transfer all of the data by DMA Transfer the last data by software Endpoint n Buffer Endpoint n Buffer 0x22 0x22 0x11 0x11 (byte 2) (byte 2) (byte 1) (byte 1) 0x33...
Page 512 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Universal Serial Bus (USB) host 32.3.11 Device disconnection The device disconnection timer starts when both the D+ and D– pins are set to LOW. If both D+ and D– remain at LOW for 2.5 µs or more, the device is considered to be disconnected.
Page 513 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Universal Serial Bus (USB) host Table 32-1. USB host registers (continued) Name Description USBHOST_INTR_USBHOST Interrupt USB host register USBHOST_INTR_USBHOST_SET Interrupt USB host set register USBHOST_INTR_USBHOST_MASK Interrupt USB host mask register USBHOST_INTR_USBHOST_MASKED Interrupt USB host masked register USBHOST_INTR_HOST_EP Interrupt USB host endpoint register...
Page 514 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture LCD direct drive LCD direct drive This PSoC™ 6 MCU reference manual provides comprehensive and detailed information about the functions of the PSoC™ 6 MCU device hardware. It is divided into two books: architecture reference manual and registers reference manual.
Page 515 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture LCD direct drive • Duty: A driver is said to operate in 1/M duty when it drives ‘M’ number of COM electrodes. Each COM electrode is effectively driven 1/M of the time. •...
Page 516 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture LCD direct drive GPIO Output Impedance ITO Panel Resistance LCD Segment Capacitance PWM Generator PWM Generator DDDD 2/3 V 1/3 V Figure 33-1. PWM drive (at 1/3 Bias) The output waveform of the drive electronics is a PWM waveform. With the Indium Tin Oxide (ITO) panel resistance and the segment capacitance to filter the PWM, the voltage across the LCD segment is an analog voltage, as shown in Figure...
Page 517 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture LCD direct drive One frame of Type A waveform (addresses all segments once) COM0 1/2 V COM1 1/2 V SEG0 1/2 V SEG1 1/2 V One Frame COM / SEG is selected COM / SEG is not selected Resulting voltage across segments = 0)
Page 518 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture LCD direct drive One frame of Type B waveform (addresses all segments twice) COM0 1/2 V COM1 1/2 V SEG0 1/2 V SEG1 1/2 V One Frame COM / SEG is selected COM / SEG is not selected Resulting voltage across segments = 0)
Page 519 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture LCD direct drive One ‘Frame’ of Type A Waveform (addresses all segments once) 2/3 V COM0 1/3 V 2/3 V COM1 1/3 V 2/3 V SEG0 1/3 V 2/3 V SEG1 1/3 V One Frame COM / SEG is selected...
Page 520 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture LCD direct drive One ‘Frame’ of Type B Waveform (addresses all segments twice) 2/3 V COM0 1/3 V 2/3 V COM1 1/3 V 2/3 V SEG0 1/3 V 2/3 V SEG1 1/3 V One Frame COM / SEG is selected...
Page 521 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture LCD direct drive The effective RMS voltage for ON and OFF segments can be calculated easily using these equations:     2 B 2 – 2 M 1 – ...
Page 522 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture LCD direct drive One ‘Frame’ of Type A Waveform (addresses all segments once) COM0 COM1 SEG0 SEG1 One Frame COM / SEG is selected COM / SEG is not selected Resulting voltage across segments = 0) Segment On: COM0 -SEG0...
Page 523 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture LCD direct drive One ‘Frame’ of Type B Waveform (addresses all segments twice) COM0 COM1 SEG0 SEG1 One Frame COM / SEG is selected COM / SEG is not selected Resulting voltage across segments = 0) Segment On: COM0 -SEG0...
Page 524 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture LCD direct drive The RMS voltage applied to on and off segments can be calculated as follows:   –     RMS OFF ------------------ -   – ...
Page 525 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture LCD direct drive Two Frames of of Type A Waveform with Dead-time (Example for 1/4 Duty and 1/3 bias) 2/3 V COM0 1/3 V 2/3 V COM1 1/3 V 2/3 V SEG0 1/3 V 2/3 V...
Page 526 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture LCD direct drive The multiplexer selects one of these two generator outputs to drive LCD, as configured by the firmware. The LCD pin logic block routes the COM and SEG outputs from the generators to the corresponding I/O matrices. Any GPIO can be used as either COM or SEG.
Page 527 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture LCD direct drive 33.3.3 Display data registers Each LCD segment pin is part of an LCD port with its own display data register, LCD0_DATAx. The device has eight such LCD ports. Note that these ports are not real pin ports but the ports/connections available in the LCD hardware for mapping the segments to commons.
Page 528 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Universal digital blocks (UDB) Universal digital blocks (UDB) This PSoC™ 6 MCU reference manual provides comprehensive and detailed information about the functions of the PSoC™ 6 MCU device hardware. It is divided into two books: architecture reference manual and registers reference manual.
Page 529 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Universal digital blocks (UDB) DSI 09 DSI 08 DSI 07 DSI 06 DSI 11 DSI 10 UDB 07 UDB 04 UDB 03 UDB 00 UDB 11 UDB 08 UDB 10 UDB 09 UDB 06 UDB 05 UDB 02...
Page 530 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Universal digital blocks (UDB) Array IN10 IN11 Carry In OUT0 OUT1 OUT2 OUT3 Carry Out OR Array Figure 34-3. PLD 12C4 structure 34.2.1.1 PLD Macrocells Figure 34-4 shows the macrocell architecture. The output drives the routing array and can be registered or combinational.
Page 531 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Universal digital blocks (UDB) PLD Macrocell Read-Only Registers The outputs of the eight macrocells in the two PLDs can be accessed by the CPU as an 8-bit read-only register. Macrocells across multiple UDBs can be accessed as 16 or 32-bit read-only registers. See “UDB addressing”...
Page 532 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Universal digital blocks (UDB) System Bus R/W Access to all registers FIFOs Output Input Muxes Muxes Input from Output to Programmable Programmable Routing Routing Data Registers To/From To/From Prev Chaining Next Datapath Datapath Accumulators...
Page 533 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Universal digital blocks (UDB) Built-in CRC/PRS The datapath has built-in support for single-cycle cyclic redundancy check (CRC) computation and pseudo random sequence (PRS) generation of arbitrary width and arbitrary polynomial specification. To achieve longer than 8-bit CRC/PRS widths, signals may be chained between datapaths.
Page 534 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Universal digital blocks (UDB) Table 34-1. Datapath working registers Type Name Description Accumulator A0, A1 The accumulators may be both a source and a destination for the ALU. They may also be loaded from a data register or a FIFO.
Page 535 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Universal digital blocks (UDB) Figure 34-7 shows the possible FIFO configurations controlled by the input/output modes. The Tx/Rx mode has one FIFO in input mode and the other in output mode. The primary example of this configuration is SPI. The dual capture configuration provides independent capture of A0 and A1, or two separately controlled captures of either A0 or A1.
Page 536 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Universal digital blocks (UDB) Table 34-3. FIFO multiplexer set in UDB CFG15 register Fx_INSEL[1:0] Description Input mode - System bus writes the FIFO, FIFO output destination is Ax or Dx. Output A0 Mode - FIFO input source is A0, FIFO output destination is the system bus. Output A1 Mode - FIFO input source is A1, FIFO output destination is the system bus.
Page 537 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Universal digital blocks (UDB) Reset Write 2 bytes Write 2 more bytes Read 3 bytes Empty = 1 Empty = 0 Empty = 0 Empty = 0 At Least Half Empty = 1 At Least Half Empty = 1 At Least Half Empty = 0 At Least Half Empty = 1...
Page 538 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Universal digital blocks (UDB) FIFO Level/Edge Write mode Two modes are available for writing the FIFO from the datapath. In the first mode, data is synchronously transferred from the accumulators to the FIFOs. The control for that write (fx_ld) is typically generated from a state machine or condition that is synchronous to the datapath clock.
Page 539 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Universal digital blocks (UDB) Chain X capxi (chaining in) capx (chaining out) read ax FIFO Cap fx_write fx_ld FIFO EDGE HFCLK (FIFO FAST) Figure 34-12. Software capture configuration FIFO control bits The Auxiliary Control (ACTL) register has four bits that may be used by the CPU firmware to control the FIFO during normal operation.
Page 540 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Universal digital blocks (UDB) System Bus async F0 (Tx) blk_stat empty empty Empty to Asynchronously cleared DP state Synch to by bus write, machine sycnhyronously set by DP read DP clk Datapath Process (Asynch) async...
Page 541 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Universal digital blocks (UDB) UDB Local Data Bus INSEL FIFO Fx FIFO Fx UDB Local Data Bus Internal Access External Access (Fx DYN = 1, dx_load = 0) (Fx DYN = 1, dx_load = 1) Figure 34-14.
Page 542 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Universal digital blocks (UDB) Arithmetic and logic operation The ALU functions, which are configured dynamically by the configuration RAM, are shown in Table 34-7. Table 34-7. ALU functions in UDB DCFG register Func[2:0] Function Operation...
Page 543 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Universal digital blocks (UDB) When a routed carry is used, the meaning with respect to each arithmetic function is shown in Table 34-10. Note that in the case of the decrement and subtract functions, the carry is active low (inverted). Table 34-10.
Page 544 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Universal digital blocks (UDB) Shift operation The shift operation occurs independent of the ALU operation, according to Table 34-12. Table 34-12. Shift operation functions in UDB DCFG register Shift[1:0] Function Pass Shift Left Shift Right Nibble Swap...
Page 545 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Universal digital blocks (UDB) Select default value or arithmetic shift Default (tie value) sor_reg shift in left (sil) Registered (sor_reg) Routed (from interconnect) Selected MSb Chained (from next datapath) shift out right (sor) Shift right or shift left (to DP output mux) Default (tie value)
Page 546 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Universal digital blocks (UDB) rad0 {0, dp_in[5:0], 0} (similar for rad1, rad2, si, ci) CFGx RAD0 MUX[2:0] These inputs are edge sensitive {0, dp_in[5:0], 0} f0_ld (similar for f1_ld, d0_ld, d1_ld) CFGx F0 LD MUX[2:0] Figure 34-17.
Page 547 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Universal digital blocks (UDB) Set msb_sel CHAIN MSB = 1 CHAIN MSB = 1 CHAIN FB = 1 CHAIN FB = 1 cmsbi cmsbo cmsbi cmsbo cmsbi cmsbo CRC data in UDB 2 UDB 1 UDB 0...
Page 548 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Universal digital blocks (UDB) Example CRC/PRS configuration The following is a summary of CRC/PRS configuration requirements, assuming that D0 is the polynomial and the CRC/PRS is computed in A0: 1. Select a suitable polynomial and write it into D0. 2.
Page 549 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Universal digital blocks (UDB) 34.2.2.7 Datapath outputs and multiplexing Conditions are generated from the registered accumulator values, ALU outputs, and FIFO status. These conditions can be driven to the digital routing for use in other UDB blocks, for use as interrupts, or to I/O pins. The 16 possible conditions are shown in Table 34-15.
Page 550 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Universal digital blocks (UDB) Output Mux dp_out[5:0] ov_ msb co_ msb cmsb sol_ msb f0_blk_stat f1_blk_stat f0_ bus_stat f1_ bus_stat Figure 34-22. Output mux connections Compares There are two compares, one of which has fixed sources (Compare 0) and the other has dynamically selectable sources (Compare 1).
Page 551 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Universal digital blocks (UDB) CFG14 CCHAIN0 ce0i (to routing (from chaining) and chaining) Compare Equal Figure 34-23. Compare equal chaining Figure 34-24 illustrates compare less than chaining. In this case, the “less than” is formed by the compare less than output in this block, which is unconditional.
Page 552 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Universal digital blocks (UDB) 34.2.2.8 Datapath parallel inputs and outputs As shown in Figure 34-25, the datapath Parallel In (PI) and Parallel Out (PO) signals give limited capability to bring routed data directly into and out of the datapath. Parallel Out signals are always available for routing as the ALU asrc selection between A0 and A1.
Page 553 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Universal digital blocks (UDB) 34.2.2.10 Dynamic configuration RAM Each datapath contains a 16 bit-by-8 word dynamic configuration RAM, which is shown in Figure 34-27. The purpose of this RAM is to control the datapath configuration bits on a cycle-by-cycle basis, based on the clock selected for that datapath.
Page 554 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Universal digital blocks (UDB) Table 34-17. Dynamic configuration quick reference (continued) Field Bits Parameter Values SRCB ALU B Input Source 00 D0 01 D1 10 A0 11 A1 SHIFT[1:0] SHIFT Function 00 PASS 01 Left Shift 10 Right Shift...
Page 555 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Universal digital blocks (UDB) Status and Control Module 7-Bit 7-Bit Period Register Mask Register (same as Mask) (same as Period) Interrupt EN/LD CTL 8-Bit 7-Bit 8-Bit From Control Register Down Count Status Register Datapath Datapath...
Page 556 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Universal digital blocks (UDB) 34.2.3.1 Status and Control mode When operating in status and control mode, this module functions as a status register, interrupt mask register, and control register in the configuration shown in Figure 34-30.
Page 557 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Universal digital blocks (UDB) Sticky status, with clear on read In this mode, the status register inputs are sampled on each cycle of the status and control clock. If the signal is high in a given sample, it is captured in the status bit and remains high, regardless of the subsequent state of the input.
Page 558 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Universal digital blocks (UDB) Table 34-19. Mode for Control Register Bit 0 in the UDB CFG18 and CFG19 registers (continued) CTL MD Description Double Sync mode Pulse mode Control Register Direct mode The default mode is Direct mode.
Page 559 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Universal digital blocks (UDB) Control Register Pulse mode Pulse mode is similar to Sync mode in that the control bit is re-sampled by the SC clock; the pulse starts on the first SC clock cycle following the bus write cycle.
Page 560 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Universal digital blocks (UDB) 34.2.3.4 Counter mode As shown in Figure 34-37, when the block is in counter mode, a 7-bit down counter is exposed for use by UDB internal operation or firmware applications. This counter has the following features: •...
Page 561 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Universal digital blocks (UDB) 34.2.3.5 Sync mode As shown in Figure 34-38, the status register can operate as a 4-bit double synchronizer, clocked by the current SC_CLK, when the SYNC MD bit in the UDB CFG22 register is set. This mode may be used to implement local synchronization of asynchronous signals, such as GPIO inputs.
Page 562 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Universal digital blocks (UDB) FIFO0 clear, FIFO1 clear The FIFO0 CLR and FIFO1 CLR bits are used to reset the state of the associated FIFO. When a ‘1’ is written to these bits, the state of the associated FIFO is cleared.
Page 563 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Universal digital blocks (UDB) 34.2.4 Reset and clock control module The primary function of the reset and clock block is to select a clock from the available global system clocks or HFCLK for each of the PLDs, the datapath, and the status and control block.
Page 564 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Universal digital blocks (UDB) 34.2.4.1 Clock control Figure 34-40 illustrates one instance of the clock selection and enable circuit. Each UDB has four of these circuits: one for each of the PLD blocks, one for the datapath, and one for the status and control block. The main components of this circuit are a global clock selection multiplexer, clock inversion, clock enable selection multiplexer, clock enable inversion, and edge detect logic.
Page 565 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Universal digital blocks (UDB) Clock Enable mode By default, the clock enable is OFF. After configuring the target block operation, software can set the mode to one of the following using the EN MODE[1:0] bits of the UDB CFG24 register shown in Figure 34-40.
Page 566 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Universal digital blocks (UDB) Compatible PLD reset control Figure 34-41 shows the compatible PLD reset system, using routed dynamic resets. PLD0 pld_routed_reset rc_in[3:0] sysreset SSEL routed CFGx CFGx reset PLD0 RES SEL[1:0] PLD0 RES POL Reset Invert Reset Select...
Page 567 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Universal digital blocks (UDB) Compatible datapath reset control Figure 34-42 shows the compatible datapath reset system, using firmware reset. The firmware reset asynchronously clears the DP output registers, the carry and shift out flags, the FIFO state, accumulators, and data registers.
Page 568 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Universal digital blocks (UDB) Compatible status and control block reset control Figure 34-43 shows the compatible status and control block reset. The mask/period and auxiliary control registers are retention registers. Aux Control (retention) sc_reset_ret sysreset_ret...
Page 569 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Universal digital blocks (UDB) Alternate PLD reset control Figure 34-44 shows the alternate PLD reset system. Although there are provisions for individual resets for each PLD, this is not supported in the PLD block. Therefore, in the alternate reset scheme, the PLD0 reset control settings applies to both PLDs.
Page 570 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Universal digital blocks (UDB) Alternate datapath reset control Figure 34-45 shows the alternate datapath reset system. The datapath routed reset applies to all datapath states, except the data registers, which are implemented as retention registers. sysreset_ret Accumulator Data Registers...
Page 571 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Universal digital blocks (UDB) Alternate status and control block reset control Figure 34-46 shows the alternate status and control block reset. The mask/period and auxiliary control registers are retention registers. sysreset_ret Aux Control Mask/Period sysreset...
Page 572 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Universal digital blocks (UDB) 34.2.5 UDB addressing The UDBs can be accessed through a number of address spaces, for 8, 16, and 32-bit accesses of both the working registers (A0, A1, D0, D1, FIFOs, and so on) and the configuration registers. •...
Page 573 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Universal digital blocks (UDB) 34.2.6.2 Coherent accumulator access (atomic reads and writes) The UDB accumulators are the primary target of data computation. Therefore, reading these registers directly during normal operation gives an undefined result, as indicated in Table 34-25.
Page 574 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Universal digital blocks (UDB) 34.3.1 PA data input logic Figure 34-48 shows the structure for the data input logic. Inputs are from each pin of an I/O port. The signal can be either single synchronized or double synchronized, or synchronization can be bypassed for asynchronous inputs.
Page 575 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Universal digital blocks (UDB) 34.3.3 PA data output logic Figure 34-50 shows the structure for the data output logic. Outputs go to each pin of an I/O port (through HSIOM). The signal can be single synchronized or synchronization can be bypassed for asynchronous outputs. Other options include the ability to output either the selected clock or an inverted version of the clock.
Page 576 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Universal digital blocks (UDB) 8 Instances (one per OE port pin input) in each Port Adapter OE selected[0] dsi_to_oe[0] OE Sync OE selected[1] To Port Pin OE[j] j = 0 to 7 OE selected[2] OE selected[3] OE MUXes...
Page 577 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Universal digital blocks (UDB) 34.3.6 PA reset multiplexer The structure of the PA reset multiplexer is shown in Figure 34-54. {dsi_xx_rc[2:0],port_xx_rc} To Input/Output reset PACFGx PACFGx RES SEL[1:0] RES INV 0: true 00: port_xx_rc 1: inverted 01: dsi_xx_rc[0]...
Page 578 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Analog subsystem Section E: Analog subsystem This section encompasses the following chapters: • “Analog reference block” on page 579 • “Low-power comparator” on page 583 • “Continuous Time Block mini (CTBm)” on page 589 •...
Page 579 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Analog reference block Analog reference block This PSoC™ 6 MCU reference manual provides comprehensive and detailed information about the functions of the PSoC™ 6 MCU device hardware. It is divided into two books: architecture reference manual and registers reference manual.
Page 580 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Analog reference block Figure 35-1 shows the architecture of the Analog Reference (AREF) block. It consists of a bandgap reference circuit, which generates 1.2 V voltage reference (VREFBG) and a positive temperature coefficient current reference (IPTAT).
Page 581 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Analog reference block 35.2.3 Zero dependency to absolute temperature current generator (I ZTAT The IZTAT current generator uses the output of the selected reference voltage (V ) to generate a precise current reference, which has a low variation over temperature.
Page 582 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Analog reference block Table 35-6. Deep Sleep mode (continued) DEEPSLEEP_MODE[1:0] Description 10 (IPTAT_IZTAT) IPTAT is ON during Deep Sleep and available to CTBm. To use this mode, IPTAT current should be redirected to IZTAT output by setting the CTB_IPTAT_REDIRECT bit of the PASS_AREF_AREF_CTRL register to ‘1’.
Page 583 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Low-power comparator Low-power comparator This PSoC™ 6 MCU reference manual provides comprehensive and detailed information about the functions of the PSoC™ 6 MCU device hardware. It is divided into two books: architecture reference manual and registers reference manual.
Page 584 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Low-power comparator 36.2 Architecture Figure 36-1 shows the block diagram for the Low-Power comparator. Low Power Comparator Block MMIO Analog Sub-Section Part of I/O Interface system Registers Routing Comparator0 Switches dsi_comp0 inp0 edge + pulse (To HSIOM or trigger...
Page 585 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Low-power comparator If the inverting input of a comparator is routed to a local voltage reference, the LPREF_EN bit in the LPCOMP_CONFIG register must be set to enable the voltage reference. 36.2.2 Output and interrupt configuration Both Comparator0 and Comparator1 have hardware outputs available at dedicated pins.
Page 586 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Low-power comparator Table 36-1. Output and interrupt configuration (continued) Register[Bit_Pos] Bit_Name Description LPCOMP_INTR[0] COMP0 Comparator0 Interrupt: hardware sets this interrupt when Comparator0 triggers. Write a '1' to clear the interrupt LPCOMP_INTR[1] COMP1 Comparator1 Interrupt: hardware sets this interrupt when Comparator1 triggers.
Page 587 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Low-power comparator 36.2.4 Hysteresis For applications that compare signals close to each other and slow changing signals, hysteresis helps to avoid oscillations at the comparator output when the signals are noisy. For such applications, a fixed hysteresis may be enabled in the comparator block.
Page 588 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Low-power comparator 36.3 Register list Table 36-4. Low-power comparator register summary Register Function LPCOMP_CONFIG LPCOMP global configuration register LPCOMP_INTR LPCOMP interrupt register LPCOMP_INTR_SET LPCOMP interrupt set register LPCOMP_INTR_MASK LPCOMP interrupt request mask register LPCOMP_INTR_MASKED LPCOMP masked interrupt output register LPCOMP_STATUS...
Page 589 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Continuous Time Block mini (CTBm) Continuous Time Block mini (CTBm) This PSoC™ 6 MCU reference manual provides comprehensive and detailed information about the functions of the PSoC™ 6 MCU device hardware. It is divided into two books: architecture reference manual and registers reference manual.
Page 590 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Continuous Time Block mini (CTBm) 37.2 Architecture Legend Firmware Controlled Switch Firmware and DSI Controlled Switch Firmware, DSI and SARSEQ Controlled Switch Switch & Opamp Control CTBm cmpout0 D 81 A 00 A 30 CA 0 A 11...
Page 591 In special instances, to connect the output to an external pin with low output drive strength or an internal load (for example, SAR ADC) with high output drive strength, switches D81/D82 shown in Figure 37-1 can be used. However, Infineon does not guarantee performance in this configuration. Reference manual 002-18176 Rev. *K 2023-07-26...
Page 592 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Continuous Time Block mini (CTBm) 37.2.2 Charge pump Each opamp includes a charge pump to get rail-to-rail input. The clock for running the charge pumps is selected using CLOCK_PUMP_PERI_SEL bits of PASS_AREF_CTRL register (see the “Analog reference block”...
Page 593 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Continuous Time Block mini (CTBm) Table 37-3. Switches and their control bits (continued) Switch Description Register Bitfield Opamp0 output to sarbus0 CTBM_OA0_SW OA0O_D51 Opamp0 - shorts low and high drive strength outputs CTBM_OA0_SW OA0O_D81 Opamp1 non-inverting input to AMUXBUS B CTBM_OA1_SW...
Page 594 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Continuous Time Block mini (CTBm) 37.2.6 Sample and hold CTBm has a sample and hold (SH) at the CTBm amplifier input, connected to the CTDAC output. This sampling is controlled by firmware. Switches also exist to route the CTDAC output to a pin without buffering, and to drive a buffered reference voltage to the CTDAC through a CTBm amplifier.
Page 595 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Continuous Time Block mini (CTBm) 37.2.7.2 Comparator interrupt The comparator output is connected to an edge detector block, which is used to detect the edge (disable/rising/falling/both) that generates interrupt. It can be configured using OAx_COMPINT bitfields in the CTBM_OA_RESx_CTRL register.
Page 596 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Continuous Time Block mini (CTBm) 37.3 Register list Table 37-5. Register summary Name Description CTBM_CTB_CTRL Global CTBm enable and power control register PASS_AREF_CTRL Global AREF control for PASS register CTBM_OA_RES0_CTRL Opamp0 control register CTBM_OA_RES1_CTRL Opamp1 control register CTBM_COMP_STAT...
Page 597 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Continuous Time DAC Continuous Time DAC This PSoC™ 6 MCU reference manual provides comprehensive and detailed information about the functions of the PSoC™ 6 MCU device hardware. It is divided into two books: architecture reference manual and registers reference manual.
Page 598 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Continuous Time DAC 38.2 Architecture CTDAC Control I/F CTDAC Core CTBm From Trigger Mux STROBE INPUT IRQ/TRIG OUT1 Double buffer DAC_ REF External Ref Output CTDAC_VAL 12-bit DAC CPU/DMA Control CTDAC_VAL_NXT CTDAC_CTRL DAC_BUF_OUT Sample/...
Page 599 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Continuous Time DAC 38.2.1 CTDAC core The CTDAC core includes the following components: • R-2R and thermometer decoder architecture with switches • Input reference selection • Output path selection • Flip-flops to register input from the control interface CTDAC Core refdrive refsense...
Page 600 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Continuous Time DAC 38.2.1.2 Input voltage reference The CTDAC can have one of the following sources as the input voltage reference: • • Internal V (buffered using CTBm opamp1) • External voltage (buffered using CTBm opamp1) Closing the CVD switch (CTDD_CVD bit [0] of CTDAC_SW register) selects V as the CTDAC voltage reference.
Page 601 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Continuous Time DAC CTBm CTDAC (D52/D62) REFDRIVE REFSENSE (A22) (A03/A13/A43) (D51) (A11) P9.2 DACOUT HOLD (A00/A20/A30) P9.6 Figure 38-5. Internal V as voltage reference Figure 38-6 shows the signal path to connect an external signal as CTDAC reference. The signal path appears similar to the internal reference signal path.
Page 602 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Continuous Time DAC Figure 38-7 shows the direct and buffered output path from the DAC. As seen, the direct path does not involve any switches from the CTBm and is completely controlled by the CTDAC switches. However, the direct path has a slower settling time for a given load (see the device datasheet for details).
Page 603 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Continuous Time DAC CTDAC CTBm (D52/D62) REFDRIVE REFSENSE (A22) (A03/A13/A43) (D51) Hold mode (A11) P9.2 DACOUT HOLD (A00/A20/A30) P9.6 Figure 38-9. Hold mode using DAC 38.2.1.4 Other configurations The CTDAC with the Opamp1 can be used to implement a PGA (see Figure 38-10).
Page 604 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Continuous Time DAC 38.2.2 CTDAC control interface The CTDAC control interface provides a digital interface to control and use the CTDAC. It offers the following features: • Support for unsigned and two’s complement numbers •...
Page 605 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Continuous Time DAC Buffered write To generate periodic waveforms, buffered write mode can be used. The CTDAC control interface provides a double buffer (CTDAC_VAL_NXT register) and a clock input (CLK) for this purpose. The data is loaded into the CTDAC_VAL_NXT register ahead of time using the CPU or the DMA and is automatically pushed into the final update register CTDAC_VAL on the rising edge of the CLK.
Page 606 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Continuous Time DAC Strobe CLK_SYS Strobe (synced – internal) CLK_PERI CTDAC_VAL_NXT Data N ignored (DAC clock input) CTDAC_VAL Data N-1 Data N DAC Analog Output Figure 38-13. Strobe edge sync write Strobe edge immediate This mode is similar to the strobe edge sync mode except that, in this mode, the CTDAC_VAL register update is initiated by the rising edge of the strobe input instead of the clock input.
Page 607 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Continuous Time DAC Strobe CLK_SYS Strobe (synced - Internal) CLK_PERI CTDAC_VAL_NXT Data N + 1 Data N ignored ignored (DAC clock input) CTDAC_VAL Data N-1 Data N Data N + 1 DAC Analog Output Figure 38-15.
Page 608 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Continuous Time DAC configurable using the DISABLED_MODE and CTDAC_RANGE bits of the CTDAC_CTRL register as shown in Table 38-1. Table 38-1. Output state OUT_EN DISABLED_MODE CTDAC_RANGE OUTPUT_STATE Tristate Programmed value The CTDAC supports two output ranges: •...
Page 609 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Continuous Time DAC 38.3 Register list Table 38-2. List of CTDAC registers Name Description CTDAC_CTRL Global CTDAC control register CTDAC_INTR CTDAC interrupt request register CTDAC_INTR_SET CTDAC interrupt request set register CTDAC_INTR_MASK CTDAC interrupt request mask CTDAC_INTR_MASKED CTDAC interrupt request masked...
Page 610 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture SAR ADC SAR ADC This PSoC™ 6 MCU reference manual provides comprehensive and detailed information about the functions of the PSoC™ 6 MCU device hardware. It is divided into two books: architecture reference manual and registers reference manual.
Page 611 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture SAR ADC 39.2 Architecture External Reference or Bypass Capacitor for Buffer Internal Reference 1.2V from AREF Pin 0 Pin 1 Pin 2 SAR_CTRL Pin 3 Pins of SARMUX Port Pin 4 Pin 5 SAR_CHAN_WORK_UPDATED SAR_CHAN_RESULT_UPDATED...
Page 612 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture SAR ADC 39.2.1.1 Single-ended and differential modes The PSoC™ 6 MCU SAR ADC can operate in single-ended and differential modes. Differential or single-ended mode can be configured using the DIFFERENTIAL_EN bitfield in the channel configuration register, SAR_CHAN_CONFIGx, where x is the channel number (0–15).
Page 613 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture SAR ADC 39.2.1.3 Result data format Result data format is configurable from two aspects: • Signed/unsigned • Left/right alignment When the result is considered signed, the most significant bit of the conversion is used for sign extension to 16 bits with MSb.
Page 614 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture SAR ADC 39.2.1.4 Negative input selection The negative input connection choice affects the voltage range and effective resolution (Table 39-2). In single- ended mode, negative input of the SAR ADC can be connected to V , or P1, P3, P5, or P7 pins of SARMUX.
Page 615 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture SAR ADC 39.2.1.5 Acquisition time Acquisition time is the time taken by sample and hold (S/H) circuit inside SAR ADC to settle. After acquisition time, the input signal source is disconnected from the SARADC core, and the output of the S/H circuit will be used for conversion.
Page 616 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture SAR ADC 39.2.1.7 SAR ADC timing Figure 39-4 shows, an ADC conversion with the minimum acquisition time of four clocks requires 18 clocks to complete. Note that the minimum acquisition time of four clock cycles at 36 MHz is based on the minimum acquisition time supported by the SAR block (R and C Figure...
Page 617 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture SAR ADC 39.2.2.1 Analog routing SARMUX has many switches that may be controlled by SARSEQ block (sequencer controller) or firmware. Different control methods have different control capability on the switches. Figure 39-5 shows the SARMUX switches.
Page 618 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture SAR ADC DSI control: Switches are controlled by DSI signals from the UDB, which can act as a secondary sequencer with a customized logic design. DSI can control most SARMUX switches. The SAR_MUX_SWITCH_DS_CTRL register can be used to enable or disable DSI control of SARMUX switches.
Page 619 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture SAR ADC Input from other pins through AMUXBUS Figure 39-7 shows how two pins that do not support SARMUX connectivity can be connected to SAR ADC as a differential pair. Additional switches are required to connect these two pins to AMUXBUS A and AMUXBUS B, and then connect AMUXBUS A and AMUXBUS B to the SAR ADC.
Page 620 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture SAR ADC Input from CTBm output via sarbus SAR ADC can be connected to CTBm output via sarbus 0/1. Figure 39-8 shows how to connect an opamp (configured as a follower) output to a single-ended SAR ADC. Figure 39-9 shows how to connect two opamp outputs to SAR ADC as a differential pair.
Page 621 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture SAR ADC P6[0] P6[1] P6[2] P6[3] P6[4] P6[5] P6[6] P6[7] Legend Unused or Open Switches Used SARMUX Switches Used CTBm Switches Unused Pin Used Pin Unused Analog Route Used Analog Route AMUXBUS B AMUXBUS A Figure 39-9.
Page 622 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture SAR ADC P6[0] P6[1] P6[2] P6[3] P6[4] P6[5] P6[6] P6[7] Legend Unused or Open Switches Used SARMUX Switches Unused Pin Used Pin Unused Analog Route Used Analog Route AMUXBUS B AMUXBUS A Figure 39-10.
Page 623 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture SAR ADC 39.2.3.2 Reference buffer and bypass capacitors The internal references, 1.2 V from bandgap and V /2, are buffered with the reference buffer. This reference may be routed to the external V pin where a capacitor can be used to filter noise that may exist on the reference.
Page 624 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture SAR ADC – One of four programmable acquisition times – Result averaging and accumulation • Scan triggering – One-shot, periodic, or continuous mode – Triggered by any digital signal or input from GPIO pin –...
Page 625 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture SAR ADC take N consecutive samples of the specified channel before moving to the next channel. In the interleaved mode, one sample is taken per channel and averaged over several scans. 39.2.4.3 Range detection The SARSEQ supports range detection to allow automatic detection of result values compared to two programmable thresholds without CPU involvement.
Page 626 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture SAR ADC 39.2.5.1 End-of-scan interrupt (EOS_INTR) After completing a scan, the end-of-scan interrupt (EOS_INTR) is raised. Firmware should clear this interrupt after picking up the data from the RESULT registers. Optionally, the EOS_INTR can also be sent out on the DSI bus by setting the EOS_DSI_OUT_EN bit in the SAR_SAMPLE_CTRL register.
Page 627 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture SAR ADC 39.2.5.5 Saturate detection interrupts The saturation detection is always applied to every conversion. This feature detects if a sample value is equal to the minimum or maximum value and sets a maskable interrupt flag for the corresponding channel. This action allows the firmware to take action, such as discarding the result, when the SAR ADC saturates.
Page 628 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture SAR ADC The CUR_AVG_ACCU and CUR_AVG_CNT fields in the SAR_AVG_STAT register indicate the current averaging accumulator contents and the current sample counter value for averaging (counts down). The SAR_MUX_SWITCH_STATUS register gives the current switch status of MUX_SWITCH0 register. These status registers help to debug SAR behavior.
Page 629 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture SAR ADC Table 39-5. Registers Register name Description SAR_MUX_SWITCH_SQ_CTRL SARMUX switch sequencer control SAR_MUX_SWITCH_STATUS SARMUX switch status Reference manual 002-18176 Rev. *K 2023-07-26...
Page 630 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Temperature sensor Temperature sensor This PSoC™ 6 MCU reference manual provides comprehensive and detailed information about the functions of the PSoC™ 6 MCU device hardware. It is divided into two books: architecture reference manual and registers reference manual.
Page 631 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Temperature sensor • ‘A’ is the 16-bit multiplier constant. The value of A is determined using the PSoC™ 6 MCU characterization data of two point slope calculation. It is calculated as given in the following equation. –...
Page 632 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Temperature sensor Note: A and B are 16-bit constants stored in flash during factory calibration. These constants are valid only with a specific SAR ADC configuration. See “SAR ADC configuration for measurement” on page 632 for details.
Page 633 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Temperature sensor 40.5 Registers Table 40-1. Registers Name Description SAR_MUX_SWITCH0 This register has the SAR_MUX_FW_TEMP_VPLUS field to connect the temperature sensor to the SAR MUX terminal. SAR_MUX_SWITCH_STATUS This register provides the status of the temperature sensor switch connection to SAR MUX.
Page 634 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Analog routing Analog routing This PSoC™ 6 MCU reference manual provides comprehensive and detailed information about the functions of the PSoC™ 6 MCU device hardware. It is divided into two books: architecture reference manual and registers reference manual.
Page 635 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Analog routing 41.2 Architecture Figure 41-1 shows the analog routing available in PSoC™ 6 MCUs. P6[0] P6[1] P6[2] P6[3] P6[4] P6[5] P6[6] P6[7] Legend GPIO Switches AMUX Splitter Switches SAR ADC Switches CTBm Switches CTDAC Switches LPCOMP Switches...
Page 636 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Analog routing Table 41-1. Available connections between PSoC™ 6 MCU analog blocks (continued) To GPIOs To SAR ADC To CTBm To LPCOMP (OA0, OA1) CTDAC CAPSENSE™ IDACs From CTDAC Through CTBm Through CTBm Internal bus AMUXBUS A...
Page 637 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture CAPSENSE™ CAPSENSE™ The CAPSENSE™ system can measure the self-capacitance of an electrode or the mutual capacitance between a pair of electrodes. In addition to capacitive sensing, the CAPSENSE™ system can function as an ADC to measure voltage on any GPIO pin that supports the CAPSENSE™...
Page 638 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Bluetooth® LE subsystem (BLESS) Section F: Bluetooth® LE subsystem (BLESS) This section has the following chapter: • “Bluetooth® Low Energy subsystem (BLESS)” on page 639 Top level architecture Bluetooth® LE subsystem block diagram Color Key: Power Modes and Bluetooth®...
Page 639 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Bluetooth® Low Energy subsystem (BLESS) Bluetooth® Low Energy subsystem (BLESS) This PSoC™ 6 MCU reference manual provides comprehensive and detailed information about the functions of the PSoC™ 6 MCU device hardware. It is divided into two books: architecture reference manual and registers reference manual.
Page 640 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Bluetooth® Low Energy subsystem (BLESS) • Radio controller: This block contains the mode transition FSM that controls the LDO and power supply switches of the radio and PHY. 43.2.1 Link layer controller This section provides details about the high-level functional modes and configuration of the link layer.
Page 641 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Bluetooth® Low Energy subsystem (BLESS) Connection state The final procedural state in the link layer protocol is the Connection state. This is entered from either the Advertising or Initiating state. The device in this state is termed as being in connection. This state has two roles: master and slave.
Page 642 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Bluetooth® Low Energy subsystem (BLESS) 43.2.3 Power states Bluetooth® LE.OFF Power applied Power removed Reset Event Bluetooth® LE.RST System reset Power Down Event asserted Reset de-asserted Firmware Action Other Event Bluetooth® LE.DPSLP System is in Active mode.
Page 643 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Bluetooth® Low Energy subsystem (BLESS) 43.2.3.3 Bluetooth® LE.DPSLP Power is supplied to logic and logic is out of reset. CLK_ECO is absent, CLK_LF is present, and CLK_AHB may be present depending on the PSoC™ power state. This is the lowest power functional mode. This mode is entered for maximum power saving during advertising/connection interval after packets transmission/reception is completed.
Page 644 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Bluetooth® Low Energy subsystem (BLESS) engine uses the parameters for radio transmit/receive. When the connection event is closed, firmware reads the status of the current connection and switches the context to the next connection in the queue. 43.2.6.1 Context switching The firmware programs parameters of a particular connection in the connection parameter memory and the event instant in the NI timer.
Page 645 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Bluetooth® Low Energy subsystem (BLESS) • The firmware reads the status of the current connection and switches the context to the next connection in the queue. 43.2.6.4 Arbitration Bluetooth® LE 4.2 states that multiple procedures can be enabled together and the radio must be arbitrated among the procedures.
Page 646 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Bluetooth® Low Energy subsystem (BLESS) The ENABLE_EXT_PA_LNA bit in the BLE_BLESS_EXT_PA_LNA_CTRL register is the master control for external PA/LNA control. • Tx ENABLE This signal will be ON during transmission and OFF when not transmitting. This signal will be active before the actual start of transmission to allow the power amplifier to ramp up.
Page 647 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Bluetooth® Low Energy subsystem (BLESS) 43.3 Register summary Table 43-2 gives the details of all register fields discussed in this chapter. For more details, see registers reference manual. Table 43-2. Register list Register Bits Field name Bit description...
Page 648 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Bluetooth® Low Energy subsystem (BLESS) Table 43-2. Register list (continued) Register Bits Field name Bit description BLE_BLELL_NI_TIMER 15:0 NI_TIMER Bluetooth® slot at which the next connection should be serviced; granularity is 625 µs. The NI timer should be programmed 1.25 ms before the connection event.
Page 649 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Bluetooth® Low Energy subsystem (BLESS) Table 43-2. Register list (continued) Register Bits Field name Bit description BLE_BLESS_EXT_PA_L ENABLE_EXT_PA_LNA When set to 1, enables the external PA and LNA NA_CTRL CHIP_EN_POL Controls the polarity of the chip enable control signal.
Page 650 PSoC™ 63 MCU with Bluetooth® LE: CY8C63x6, CY8C63x7 architecture Revision history Revision history Document Date of release Description of changes version 2016-12-22 Initial version of reference manual Updates to the Nonvolatile Memory Programming, Power Supply and 2017-03-08 Monitoring, and Device Power Modes chapters Added the eFuse chapter.
Page 651 38. 2020-07-03 Aligned the Introduction section with the datasheet. Updates throughout the document to address review comments. Migrated to Infineon template Fixed typos: Sflash to SFlash, AUXflash and EE emulation to AUXFlash. Added Bluetooth® feature in “Features” on page 16 and “Features”...
Page 652 Technologies hereby disclaims any and all warranties authorized representatives of Infineon Technologies, and liabilities of any kind, including without limitation Infineon Technologies’ products may not be used in warranties of non-infringement of intellectual any applications where a failure of the product or any property rights of any third party.

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