Power Cycle Mode Programming - Infineon PSoC 4 Quick Start Quide

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PSoC 4 Programming Using an External Microcontroller (HSSP)

Power Cycle Mode Programming

8
Power Cycle Mode Programming
Device programming starts with a device reset to acquire the device and enter programming mode. The
recommended method of resetting the device from the host side is to toggle the device XRES pin. But some
lower pin count devices in the PSoC 4000 family do not have an XRES pin, and the host has to toggle the device
V
pin to reset the device (power cycle mode). All the projects provided with the application note work using
dd
the XRES programming mode because the PSoC 5LP host processor on the development kit does not have the
hardware connections to toggle the power supply of the target PSoC 4 device. So, when porting the projects to
your host processor and adding power cycle mode support, the following changes and considerations need to
be made in the project.
1. The DEVICE_ACQUIRE_TIMEOUT value, discussed in the section DEVICE_ACQUIRE_TIMEOUT, has to be
modified to reflect the much longer 30-ms timeout window required for power cycle mode programming.
So, for example, if the DEVICE_ACQUIRE_TIMEOUT define has been calculated to be 20 for a 2 ms XRES
mode acquire timing, then that define should be changed to 300 for a 30 ms power cycle mode acquire
timing.
2. The function definitions related to toggling of the XRES pin on the host side should be modified as
appropriate to toggle the device power rails. These functions are - SetXresHigh(),SetXresLow().
3. If an I/O pin of the host processor is used to power the PSoC 4 device directly to toggle the power from the
host side, ensure that the I/O pin can source the current required for device operation as specified in the
respective PSoC 4 device datasheet. If the I/O pin is not able to source the required current, the output
voltage (V
) typically decreases, and can potentially go even below the minimum PSoC 4 device operating
OH
voltage. This can cause programming failures. Such a voltage droop scenario can be identified by observing
the power rail voltages on the oscilloscope.
Application Note
20 of 45
001-84858 Rev. *N
2021-03-23

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