Appendix B: Status Codes For Srom Request - Infineon PSoC 4 Quick Start Quide

PSoC 4 Programming Using an External Microcontroller (HSSP)

Appendix B: Status Codes for SROM Request

15 Appendix B: Status Codes for SROM Request
All programming-related operations are implemented as system call functions. They are executed out of the
SROM in the privileged mode of operation.
You have no access to read or modify the SROM code. The DAP or the Cortex-M0 CPU requests the system call
by writing the function opcode and function parameters to certain registers and then requesting the SROM to
execute the function. Based on the function opcode, the SROM executes the corresponding system call from its
memory and updates the function execution status in a register. The DAP or the CPU should read this status
register for the pass/fail result of the function execution.
When SROM_SYSREQ_BIT (bit 31) and SROM_PRIVILEGED_BIT (bit 28) of the CPUSS_SYSREQ register are
cleared, that indicates the completion of the system call. The CPUSS_SYSARG register is read to check the
success or failure status of the system call.
If the 32-bit value read from the register is 0xAXXXXXXX (X denotes don't care values), the system call was
successful. If the value read from the register is in the form 0xF00000YY, it indicates failure, and YY indicates the
reason for failure. Table 12
For more details, see the "Nonvolatile Memory Programming" chapters of the respective PSoC 4 Architecture
Technical Reference Manuals (TRM) listed in the
Table 12 Error Status Codes and Reason for Failure
Status Code
(32-Bit Value in
CPUSS_SYSARG
Register)
0xAXXXXXXX
0x F0000001
0x F0000003
0x F0000004
0x F0000005
0x F0000006
0x F0000007
0x F0000008
0x F0000009
0x F000000A
0x F000000B
0x F000000C
0x F000000E
Application Note
shows the list of error codes.
Related Documentation
Description
Success. The value "X" denotes the "don't care" value, which contains 0 as
returned by the SROM unless the API returns the parameter directly to the
CPUSS_SYSARG register.
Invalid Chip Protection Mode: This API is not available during the current chip
protection mode.
Invalid Page Latch Address: The address within the page latch buffer is either out
of bounds or the size provided is too large for the page address.
Invalid Address: The row ID or byte address provided is outside the available
memory.
Row Protected: The row ID provided is that of a protected row.
SRAM Address Invalid: The SRAM address is out of bounds.
Resume Completed: All non-blocking APIs have been completed. The resume API
cannot be called until the next non-blocking API.
Pending Resume: A non-blocking API was initiated, and it must be completed by
calling the resume API before any other APIs may be called.
System Call Still In Progress: A resume or non-blocking API is still in progress. The
SPC ISR must fire before attempting the next resume.
Checksum Zero Failed: The calculated checksum was not zero.
Invalid Opcode: The opcode is not a valid API opcode.
Key Opcode Mismatch; The opcode provided does not match key1 and key2.
Invalid Start Address: The start address is greater than the end address provided.
section.
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