Appendix C: Bit Field Definitions Of Hssp Error Status Register; Bits[2:0] - Swd Acknowledge Response (Swd Ack [2:0]); Bit 3 - Swd Read Data Parity Error; Bit 4 - Port Acquire Timeout - Infineon PSoC 4 Quick Start Quide

PSoC 4 Programming Using an External Microcontroller (HSSP)

Appendix C: Bit Field Definitions of HSSP Error Status Register

16 Appendix C: Bit Field Definitions of HSSP Error Status Register
The HSSP Error Status Register contains the status of the current HSSP operation. When any of the top-level
steps in the HSSP application returns a failure status, the ReadHsspErrorStatus() function is called from
the main application code to get the details of the error. This function returns the contents of this register. See
Figure 2 for the bit fields returned by this function.
For a successful HSSP operation, all bits except bit 0 of this 8-bit register must be zero. If bit 0 is set, it indicates
that the SWD packet received an OK ACK, as
16.1 Bits[2:0] – SWD Acknowledge Response (SWD ACK [2:0])
This is the 3-bit acknowledgment response for an SWD packet sent by the target device to the host
programmer. The possible ACK codes are listed:
Table 13 SWD ACK Response Codes
ACK[2:0] ACK Response
Meaning
001 OK (SUCCESS)
010 WAIT
100 FAULT
Any other Undefined code
code
All the responses except the OK ACK response require that the host abort the HSSP operation and restart from
the first step. Even for an OK ACK, the rest of the bit fields (bits 3 to 6) in the status register in
not be set. If any of the other bit fields are set even with the OK ACK, the HSSP operation must be aborted and
restarted.
WAIT ACK is received if the host programmer tries to clock SWDCK at a frequency higher than the maximum
specified value of SWDCK in the programming specifications.
16.2 Bit 3 – SWD Read Data Parity Error
The host programmer sets this bit if a parity error occurs in the data received from the target device. The host
must abort the HSSP operation and try again.
16.3 Bit 4 – Port Acquire Timeout
This bit is set if the SWD packets that are part of acquiring the target device (Step 1. The
DeviceAcquire()function in the ProgrammingSteps.c file) are not completed successfully. If this bit is set,
the HSSP operation must be aborted and retried.
There are two possible causes for this timeout error: Either the hardware connection fails between the host
programmer and the target device, or the host programmer fails to meet the timing requirements to enter the
target device programming mode.
For details on the timing requirements to enter the PSoC 4 programming mode, see "Step 1: Acquire Chip" in
the programming specifications document of the respective device listed in the
section.
Application Note
Table 13 shows.
Description
This means that a previous SWD transaction was successful.
This error code indicates that the target has returned five WAIT ACK
responses consecutively.
This error code indicates that there is a parity error in the 4-byte data
packet sent by the host during the previous SWD write packet.
Treat this as a FAULT response.
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Figure 2 should
Related Documentation
001-84858 Rev. *N
2021-03-23