Infineon PSoC 4000 Series Technical Reference Manual
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Infineon PSoC 4000 Series Technical Reference Manual

Infineon PSoC 4000 Series Technical Reference Manual

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Summary of Contents for Infineon PSoC 4000 Series

  • Page 1 The document following this cover page is marked as “Cypress” document as this is the company that originally developed the product. Please note that Infineon will continue to offer the product to new and existing customers as part of the Infineon product portfolio.
  • Page 2 PSoC 4000 TRM PSoC 4000 Family ® PSoC 4 Registers Technical Reference Manual (TRM) Document Number: 001-90002 Rev. *E March 15, 2019 Cypress Semiconductor 198 Champion Court San Jose, CA 95134-1709 Phone: +1.408.943.2600 www.cypress.com...
  • Page 3 Copyrights © Cypress Semiconductor Corporation, 2013-2019. This document is the property of Cypress Semiconductor Corporation and its subsidiaries ("Cypress"). This document, including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries worldwide.

  • Page 4: Table Of Contents

    Contents Register Mapping CM0 Registers ..........................5 CPUSS Registers ........................68 GPIO Registers ......................... 81 HSIOM Registers ........................114 PERI Registers ........................125 SCB Registers ......................... 130 SFLASH Registers ........................185 SPCIF Registers ........................202 SRSSLT Registers ........................209 10. TCPWM Registers ........................242 11.

  • Page 5: Register Mapping

    Register Mapping The Register Mapping section discusses the registers of the PSoC 4 device. It lists all the registers in mapping tables, in address order. Register General Conventions The register conventions specific to this section and the Register Reference chapter are listed in this table. Convention Example Description...

  • Page 6: Cm0 Registers

    CM0 Registers This section discusses the CM0 registers of PSoC 4 device. It lists all the registers in mapping tables, in address order. CM0 Register Details Register Address Description CM0_DWT_PID4 0xE0001FD0 Watchpoint Unit CoreSight ROM Table Peripheral ID #4 CM0_DWT_PID0 0xE0001FE0 Watchpoint Unit CoreSight ROM Table Peripheral ID #0 CM0_DWT_PID1...
  • Page 7 Register Address Description CM0_IPR2 0xE000E408 Interrupt Priority Registers. See CM0_IPR0 for the details of bit fields. CM0_IPR3 0xE000E40C Interrupt Priority Registers. See CM0_IPR0 for the details of bit fields. CM0_IPR4 0xE000E410 Interrupt Priority Registers. See CM0_IPR0 for the details of bit fields. CM0_IPR5 0xE000E414 Interrupt Priority Registers.
  • Page 8 CM0_DWT_PID4 1.1.1 CM0_DWT_PID4 Address = 0xE0001FD0 Watchpoint Unit CoreSight ROM Table Peripheral ID #4 Address: 0xE0001FD0 Retention: Retained Bits SW Access HW Access Name VALUE [7:0] Bits SW Access HW Access Name VALUE [15:8] Bits SW Access HW Access Name VALUE [23:16] Bits SW Access...
  • Page 9 CM0_DWT_PID0 1.1.2 CM0_DWT_PID0 Address = 0xE0001FE0 Watchpoint Unit CoreSight ROM Table Peripheral ID #0 Address: 0xE0001FE0 Retention: Retained Bits SW Access HW Access Name VALUE [7:0] Bits SW Access HW Access Name VALUE [15:8] Bits SW Access HW Access Name VALUE [23:16] Bits SW Access...
  • Page 10 CM0_DWT_PID1 1.1.3 CM0_DWT_PID1 Address = 0xE0001FE4 Watchpoint Unit CoreSight ROM Table Peripheral ID #1 Address: 0xE0001FE4 Retention: Retained Bits SW Access HW Access Name VALUE [7:0] Bits SW Access HW Access Name VALUE [15:8] Bits SW Access HW Access Name VALUE [23:16] Bits SW Access...
  • Page 11 CM0_DWT_PID2 1.1.4 CM0_DWT_PID2 Address = 0xE0001FE8 Watchpoint Unit CoreSight ROM Table Peripheral ID #2 Address: 0xE0001FE8 Retention: Retained Bits SW Access HW Access Name VALUE [7:0] Bits SW Access HW Access Name VALUE [15:8] Bits SW Access HW Access Name VALUE [23:16] Bits SW Access...
  • Page 12 CM0_DWT_PID3 1.1.5 CM0_DWT_PID3 Address = 0xE0001FEC Watchpoint Unit CoreSight ROM Table Peripheral ID #3 Address: 0xE0001FEC Retention: Retained Bits SW Access HW Access Name VALUE [7:0] Bits SW Access HW Access Name VALUE [15:8] Bits SW Access HW Access Name VALUE [23:16] Bits SW Access...
  • Page 13 CM0_DWT_CID0 1.1.6 CM0_DWT_CID0 Address = 0xE0001FF0 Watchpoint Unit CoreSight ROM Table Component ID #0 Address: 0xE0001FF0 Retention: Retained Bits SW Access HW Access Name VALUE [7:0] Bits SW Access HW Access Name VALUE [15:8] Bits SW Access HW Access Name VALUE [23:16] Bits SW Access...
  • Page 14 CM0_DWT_CID1 1.1.7 CM0_DWT_CID1 Address = 0xE0001FF4 Watchpoint Unit CoreSight ROM Table Component ID #1 Address: 0xE0001FF4 Retention: Retained Bits SW Access HW Access Name VALUE [7:0] Bits SW Access HW Access Name VALUE [15:8] Bits SW Access HW Access Name VALUE [23:16] Bits SW Access...
  • Page 15 CM0_DWT_CID2 1.1.8 CM0_DWT_CID2 Address = 0xE0001FF8 Watchpoint Unit CoreSight ROM Table Component ID #2 Address: 0xE0001FF8 Retention: Retained Bits SW Access HW Access Name VALUE [7:0] Bits SW Access HW Access Name VALUE [15:8] Bits SW Access HW Access Name VALUE [23:16] Bits SW Access...
  • Page 16 CM0_DWT_CID3 1.1.9 CM0_DWT_CID3 Address = 0xE0001FFC Watchpoint Unit CoreSight ROM Table Component ID #3 Address: 0xE0001FFC Retention: Retained Bits SW Access HW Access Name VALUE [7:0] Bits SW Access HW Access Name VALUE [15:8] Bits SW Access HW Access Name VALUE [23:16] Bits SW Access...
  • Page 17 CM0_BP_PID4 1.1.10 CM0_BP_PID4 Address = 0xE0002FD0 Breakpoint Unit CoreSight ROM Table Peripheral ID #4 Address: 0xE0002FD0 Retention: Retained Bits SW Access HW Access Name VALUE [7:0] Bits SW Access HW Access Name VALUE [15:8] Bits SW Access HW Access Name VALUE [23:16] Bits SW Access...
  • Page 18 CM0_BP_PID0 1.1.11 CM0_BP_PID0 Address = 0xE0002FE0 Breakpoint Unit CoreSight ROM Table Peripheral ID #0 Address: 0xE0002FE0 Retention: Retained Bits SW Access HW Access Name VALUE [7:0] Bits SW Access HW Access Name VALUE [15:8] Bits SW Access HW Access Name VALUE [23:16] Bits SW Access...
  • Page 19 CM0_BP_PID1 1.1.12 CM0_BP_PID1 Address = 0xE0002FE4 Breakpoint Unit CoreSight ROM Table Peripheral ID #1 Address: 0xE0002FE4 Retention: Retained Bits SW Access HW Access Name VALUE [7:0] Bits SW Access HW Access Name VALUE [15:8] Bits SW Access HW Access Name VALUE [23:16] Bits SW Access...
  • Page 20 CM0_BP_PID2 1.1.13 CM0_BP_PID2 Address = 0xE0002FE8 Breakpoint Unit CoreSight ROM Table Peripheral ID #2 Address: 0xE0002FE8 Retention: Retained Bits SW Access HW Access Name VALUE [7:0] Bits SW Access HW Access Name VALUE [15:8] Bits SW Access HW Access Name VALUE [23:16] Bits SW Access...
  • Page 21 CM0_BP_PID3 1.1.14 CM0_BP_PID3 Address = 0xE0002FEC Breakpoint Unit CoreSight ROM Table Peripheral ID #3 Address: 0xE0002FEC Retention: Retained Bits SW Access HW Access Name VALUE [7:0] Bits SW Access HW Access Name VALUE [15:8] Bits SW Access HW Access Name VALUE [23:16] Bits SW Access...
  • Page 22 CM0_BP_CID0 1.1.15 CM0_BP_CID0 Address = 0xE0002FF0 Breakpoint Unit CoreSight ROM Table Component ID #0 Address: 0xE0002FF0 Retention: Retained Bits SW Access HW Access Name VALUE [7:0] Bits SW Access HW Access Name VALUE [15:8] Bits SW Access HW Access Name VALUE [23:16] Bits SW Access...
  • Page 23 CM0_BP_CID1 1.1.16 CM0_BP_CID1 Address = 0xE0002FF4 Breakpoint Unit CoreSight ROM Table Component ID #1 Address: 0xE0002FF4 Retention: Retained Bits SW Access HW Access Name VALUE [7:0] Bits SW Access HW Access Name VALUE [15:8] Bits SW Access HW Access Name VALUE [23:16] Bits SW Access...
  • Page 24 CM0_BP_CID2 1.1.17 CM0_BP_CID2 Address = 0xE0002FF8 Breakpoint Unit CoreSight ROM Table Component ID #2 Address: 0xE0002FF8 Retention: Retained Bits SW Access HW Access Name VALUE [7:0] Bits SW Access HW Access Name VALUE [15:8] Bits SW Access HW Access Name VALUE [23:16] Bits SW Access...
  • Page 25 CM0_BP_CID3 1.1.18 CM0_BP_CID3 Address = 0xE0002FFC Breakpoint Unit CoreSight ROM Table Component ID #3 Address: 0xE0002FFC Retention: Retained Bits SW Access HW Access Name VALUE [7:0] Bits SW Access HW Access Name VALUE [15:8] Bits SW Access HW Access Name VALUE [23:16] Bits SW Access...
  • Page 26 CM0_SYST_CSR 1.1.19 CM0_SYST_CSR Address = 0xE000E010 SysTick Control & Status Address: 0xE000E010 Retention: Retained Bits SW Access None HW Access None Name CLK- None [7:3] TICKINT ENABLE SOURCE Bits SW Access None HW Access None Name None [15:8] Bits SW Access None HW Access None...
  • Page 27 CM0_SYST_CSR 1.1.19 CM0_SYST_CSR (continued) CLKSOURCE Indicates the SysTick counter clock source: '0': SysTick uses the low frequency clock "clk_lf". For this mode to function, "clk_lf" should be less than half the frequency of "clk_sys". Note that "clk_lf" is generated by a low accuracy ILO (Internal Low power Oscillator), with a target frequency of 32.768 kHz (frequency can be as low as 15 KHz and as high as 60 kHz).
  • Page 28 CM0_SYST_RVR 1.1.20 CM0_SYST_RVR Address = 0xE000E014 SysTick Reload Value Address: 0xE000E014 Retention: Retained Bits SW Access HW Access Name RELOAD [7:0] Bits SW Access HW Access Name RELOAD [15:8] Bits SW Access HW Access Name RELOAD [23:16] Bits SW Access None HW Access None...
  • Page 29 CM0_SYST_CVR 1.1.21 CM0_SYST_CVR Address = 0xE000E018 SysTick Current Value Address: 0xE000E018 Retention: Retained Bits SW Access HW Access Name CURRENT [7:0] Bits SW Access HW Access Name CURRENT [15:8] Bits SW Access HW Access Name CURRENT [23:16] Bits SW Access None HW Access None...
  • Page 30 CM0_SYST_CALIB 1.1.22 CM0_SYST_CALIB Address = 0xE000E01C SysTick Calibration Value Address: 0xE000E01C Retention: Retained Bits SW Access HW Access Name TENMS [7:0] Bits SW Access HW Access Name TENMS [15:8] Bits SW Access HW Access Name TENMS [23:16] Bits SW Access None HW Access None...
  • Page 31 CM0_SYST_CALIB 1.1.22 CM0_SYST_CALIB (continued) 23 : 0 TENMS Optionally, holds a reload value to be used for 10ms (100Hz) timing, subject to system clock skew errors. If this field is "0", the calibration value is not known. In PSoC4A-BLE (and later products), SysTick counter functionality on the low frequency clock is provided and this field is 0x00:00147.
  • Page 32 CM0_ISER 1.1.23 CM0_ISER Address = 0xE000E100 Interrupt Set-Enable Register Address: 0xE000E100 Retention: Retained Bits SW Access RW1S HW Access Name SETENA [7:0] Bits SW Access RW1S HW Access Name SETENA [15:8] Bits SW Access RW1S HW Access Name SETENA [23:16] Bits SW Access RW1S...
  • Page 33 CM0_ICER 1.1.24 CM0_ICER Address = 0xE000E180 Interrupt Clear Enable Register Address: 0xE000E180 Retention: Retained Bits SW Access RW1C HW Access Name CLRENA [7:0] Bits SW Access RW1C HW Access Name CLRENA [15:8] Bits SW Access RW1C HW Access Name CLRENA [23:16] Bits SW Access RW1C...
  • Page 34 CM0_ISPR 1.1.25 CM0_ISPR Address = 0xE000E200 Interrupt Set-Pending Register Address: 0xE000E200 Retention: Retained Bits SW Access RW1S HW Access Name SETPEND [7:0] Bits SW Access RW1S HW Access Name SETPEND [15:8] Bits SW Access RW1S HW Access Name SETPEND [23:16] Bits SW Access RW1S...
  • Page 35 CM0_ICPR 1.1.26 CM0_ICPR Address = 0xE000E280 Interrupt Clear-Pending Register Address: 0xE000E280 Retention: Retained Bits SW Access RW1C HW Access Name CLRPEND [7:0] Bits SW Access RW1C HW Access Name CLRPEND [15:8] Bits SW Access RW1C HW Access Name CLRPEND [23:16] Bits SW Access RW1C...
  • Page 36 CM0_IPR0 1.1.27 CM0_IPR0 Address = 0xE000E400 Interrupt Priority Registers Address: 0xE000E400 Retention: Retained Bits SW Access None HW Access None Name PRI_N0 [7:6] None [5:0] Bits SW Access None HW Access None Name PRI_N1 [15:14] None [13:8] Bits SW Access None HW Access None...
  • Page 37 CM0_CPUID 1.1.28 CM0_CPUID Address = 0xE000ED00 CPUID Register Address: 0xE000ED00 Retention: Retained Bits SW Access HW Access Name PARTNO [7:4] REVISION [3:0] Bits SW Access HW Access Name PARTNO [15:8] Bits SW Access HW Access Name VARIANT [23:20] CONSTANT [19:16] Bits SW Access HW Access...
  • Page 38 CM0_ICSR 1.1.29 CM0_ICSR Address = 0xE000ED04 Interrupt Control State Register Address: 0xE000ED04 Retention: Retained Bits SW Access HW Access Name VECTACTIVE [7:0] Bits SW Access None HW Access None Name VECTAC- VECTPENDING [15:12] None [11:9] TIVE Bits SW Access None HW Access None Name...
  • Page 39 CM0_ICSR 1.1.29 CM0_ICSR (continued) ISRPREEMPT Indicates whether a pending exception will be serviced on exit from debug halt state. Default Value: 0 ISRPENDING Indicates if an external configurable, NVIC generated, interrupt is pending. Default Value: 0 20 : 12 VECTPENDING The exception number for the highest priority pending exception.
  • Page 40 CM0_AIRCR 1.1.30 CM0_AIRCR Address = 0xE000ED0C Application Interrupt and Reset Control Register Address: 0xE000ED0C Retention: Retained Bits SW Access None RW1S RW1C None HW Access None None Name SYSRESE- VECTCL- None [7:3] None TREQ RACTIVE Bits SW Access None HW Access None Name ENDIAN-...
  • Page 41 CM0_SCR 1.1.31 CM0_SCR Address = 0xE000ED10 System Control Register Address: 0xE000ED10 Retention: Retained Bits SW Access None None None HW Access None None None Name SEVON- SLEEP- SLEEPON- None [7:5] None None PEND DEEP EXIT Bits SW Access None HW Access None Name None [15:8]...
  • Page 42 CM0_CCR 1.1.32 CM0_CCR Address = 0xE000ED14 Configuration and Control Register Address: 0xE000ED14 Retention: Retained Bits SW Access None None HW Access None None Name None [7:4] ALIGN_TR None Bits SW Access None None HW Access None None Name None [15:10] STKALIGN None Bits...
  • Page 43 CM0_SHPR2 1.1.33 CM0_SHPR2 Address = 0xE000ED1C System Handler Priority Register 2 Address: 0xE000ED1C Retention: Retained Bits SW Access None HW Access None Name None [7:0] Bits SW Access None HW Access None Name None [15:8] Bits SW Access None HW Access None Name None [23:16]...
  • Page 44 CM0_SHPR3 1.1.34 CM0_SHPR3 Address = 0xE000ED20 System Handler Priority Register 3 Address: 0xE000ED20 Retention: Retained Bits SW Access None HW Access None Name None [7:0] Bits SW Access None HW Access None Name None [15:8] Bits SW Access None HW Access None Name PRI_14 [23:22]...
  • Page 45 CM0_SHCSR 1.1.35 CM0_SHCSR Address = 0xE000ED24 System Handler Control and State Register Address: 0xE000ED24 Retention: Retained Bits SW Access None HW Access None Name None [7:0] Bits SW Access None HW Access None Name SVCALL- None PENDED Bits SW Access None HW Access None...
  • Page 46 CM0_SCS_PID4 1.1.36 CM0_SCS_PID4 Address = 0xE000EFD0 System Control Space ROM Table Peripheral ID #4 Address: 0xE000EFD0 Retention: Retained Bits SW Access HW Access Name VALUE [7:0] Bits SW Access HW Access Name VALUE [15:8] Bits SW Access HW Access Name VALUE [23:16] Bits SW Access...
  • Page 47 CM0_SCS_PID0 1.1.37 CM0_SCS_PID0 Address = 0xE000EFE0 System Control Space ROM Table Peripheral ID #0 Address: 0xE000EFE0 Retention: Retained Bits SW Access HW Access Name VALUE [7:0] Bits SW Access HW Access Name VALUE [15:8] Bits SW Access HW Access Name VALUE [23:16] Bits SW Access...
  • Page 48 CM0_SCS_PID1 1.1.38 CM0_SCS_PID1 Address = 0xE000EFE4 System Control Space ROM Table Peripheral ID #1 Address: 0xE000EFE4 Retention: Retained Bits SW Access HW Access Name VALUE [7:0] Bits SW Access HW Access Name VALUE [15:8] Bits SW Access HW Access Name VALUE [23:16] Bits SW Access...
  • Page 49 CM0_SCS_PID2 1.1.39 CM0_SCS_PID2 Address = 0xE000EFE8 System Control Space ROM Table Peripheral ID #2 Address: 0xE000EFE8 Retention: Retained Bits SW Access HW Access Name VALUE [7:0] Bits SW Access HW Access Name VALUE [15:8] Bits SW Access HW Access Name VALUE [23:16] Bits SW Access...
  • Page 50 CM0_SCS_PID3 1.1.40 CM0_SCS_PID3 Address = 0xE000EFEC System Control Space ROM Table Peripheral ID #3 Address: 0xE000EFEC Retention: Retained Bits SW Access HW Access Name VALUE [7:0] Bits SW Access HW Access Name VALUE [15:8] Bits SW Access HW Access Name VALUE [23:16] Bits SW Access...
  • Page 51 CM0_SCS_CID0 1.1.41 CM0_SCS_CID0 Address = 0xE000EFF0 System Control Space ROM Table Component ID #0 Address: 0xE000EFF0 Retention: Retained Bits SW Access HW Access Name VALUE [7:0] Bits SW Access HW Access Name VALUE [15:8] Bits SW Access HW Access Name VALUE [23:16] Bits SW Access...
  • Page 52 CM0_SCS_CID1 1.1.42 CM0_SCS_CID1 Address = 0xE000EFF4 System Control Space ROM Table Component ID #1 Address: 0xE000EFF4 Retention: Retained Bits SW Access HW Access Name VALUE [7:0] Bits SW Access HW Access Name VALUE [15:8] Bits SW Access HW Access Name VALUE [23:16] Bits SW Access...
  • Page 53 CM0_SCS_CID2 1.1.43 CM0_SCS_CID2 Address = 0xE000EFF8 System Control Space ROM Table Component ID #2 Address: 0xE000EFF8 Retention: Retained Bits SW Access HW Access Name VALUE [7:0] Bits SW Access HW Access Name VALUE [15:8] Bits SW Access HW Access Name VALUE [23:16] Bits SW Access...
  • Page 54 CM0_SCS_CID3 1.1.44 CM0_SCS_CID3 Address = 0xE000EFFC System Control Space ROM Table Component ID #3 Address: 0xE000EFFC Retention: Retained Bits SW Access HW Access Name VALUE [7:0] Bits SW Access HW Access Name VALUE [15:8] Bits SW Access HW Access Name VALUE [23:16] Bits SW Access...
  • Page 55 CM0_ROM_SCS 1.1.45 CM0_ROM_SCS Address = 0xE00FF000 CM0 CoreSight ROM Table Peripheral #0 Address: 0xE00FF000 Retention: Retained Bits SW Access HW Access Name VALUE [7:0] Bits SW Access HW Access Name VALUE [15:8] Bits SW Access HW Access Name VALUE [23:16] Bits SW Access HW Access...
  • Page 56 CM0_ROM_DWT 1.1.46 CM0_ROM_DWT Address = 0xE00FF004 CM0 CoreSight ROM Table Peripheral #1 Address: 0xE00FF004 Retention: Retained Bits SW Access HW Access Name VALUE [7:0] Bits SW Access HW Access Name VALUE [15:8] Bits SW Access HW Access Name VALUE [23:16] Bits SW Access HW Access...
  • Page 57 CM0_ROM_BPU 1.1.47 CM0_ROM_BPU Address = 0xE00FF008 CM0 CoreSight ROM Table Peripheral #2 Address: 0xE00FF008 Retention: Retained Bits SW Access HW Access Name VALUE [7:0] Bits SW Access HW Access Name VALUE [15:8] Bits SW Access HW Access Name VALUE [23:16] Bits SW Access HW Access...
  • Page 58 CM0_ROM_END 1.1.48 CM0_ROM_END Address = 0xE00FF00C CM0 CoreSight ROM Table End Marker Address: 0xE00FF00C Retention: Retained Bits SW Access HW Access Name VALUE [7:0] Bits SW Access HW Access Name VALUE [15:8] Bits SW Access HW Access Name VALUE [23:16] Bits SW Access HW Access...
  • Page 59 CM0_ROM_CSMT 1.1.49 CM0_ROM_CSMT Address = 0xE00FFFCC CM0 CoreSight ROM Table Memory Type Address: 0xE00FFFCC Retention: Retained Bits SW Access HW Access Name VALUE [7:0] Bits SW Access HW Access Name VALUE [15:8] Bits SW Access HW Access Name VALUE [23:16] Bits SW Access HW Access...
  • Page 60 CM0_ROM_PID4 1.1.50 CM0_ROM_PID4 Address = 0xE00FFFD0 CM0 CoreSight ROM Table Peripheral ID #4 Address: 0xE00FFFD0 Retention: Retained Bits SW Access HW Access Name VALUE [7:0] Bits SW Access HW Access Name VALUE [15:8] Bits SW Access HW Access Name VALUE [23:16] Bits SW Access HW Access...
  • Page 61 CM0_ROM_PID0 1.1.51 CM0_ROM_PID0 Address = 0xE00FFFE0 CM0 CoreSight ROM Table Peripheral ID #0 Address: 0xE00FFFE0 Retention: Retained Bits SW Access HW Access Name VALUE [7:0] Bits SW Access HW Access Name VALUE [15:8] Bits SW Access HW Access Name VALUE [23:16] Bits SW Access HW Access...
  • Page 62 CM0_ROM_PID1 1.1.52 CM0_ROM_PID1 Address = 0xE00FFFE4 CM0 CoreSight ROM Table Peripheral ID #1 Address: 0xE00FFFE4 Retention: Retained Bits SW Access HW Access Name VALUE [7:0] Bits SW Access HW Access Name VALUE [15:8] Bits SW Access HW Access Name VALUE [23:16] Bits SW Access HW Access...
  • Page 63 CM0_ROM_PID2 1.1.53 CM0_ROM_PID2 Address = 0xE00FFFE8 CM0 CoreSight ROM Table Peripheral ID #2 Address: 0xE00FFFE8 Retention: Retained Bits SW Access HW Access Name VALUE [7:0] Bits SW Access HW Access Name VALUE [15:8] Bits SW Access HW Access Name VALUE [23:16] Bits SW Access HW Access...
  • Page 64 CM0_ROM_PID3 1.1.54 CM0_ROM_PID3 Address = 0xE00FFFEC CM0 CoreSight ROM Table Peripheral ID #3 Address: 0xE00FFFEC Retention: Retained Bits SW Access HW Access Name VALUE [7:0] Bits SW Access HW Access Name VALUE [15:8] Bits SW Access HW Access Name VALUE [23:16] Bits SW Access HW Access...
  • Page 65 CM0_ROM_CID0 1.1.55 CM0_ROM_CID0 Address = 0xE00FFFF0 CM0 CoreSight ROM Table Component ID #0 Address: 0xE00FFFF0 Retention: Retained Bits SW Access HW Access Name VALUE [7:0] Bits SW Access HW Access Name VALUE [15:8] Bits SW Access HW Access Name VALUE [23:16] Bits SW Access HW Access...
  • Page 66 CM0_ROM_CID1 1.1.56 CM0_ROM_CID1 Address = 0xE00FFFF4 CM0 CoreSight ROM Table Component ID #1 Address: 0xE00FFFF4 Retention: Retained Bits SW Access HW Access Name VALUE [7:0] Bits SW Access HW Access Name VALUE [15:8] Bits SW Access HW Access Name VALUE [23:16] Bits SW Access HW Access...
  • Page 67 CM0_ROM_CID2 1.1.57 CM0_ROM_CID2 Address = 0xE00FFFF8 CM0 CoreSight ROM Table Component ID #2 Address: 0xE00FFFF8 Retention: Retained Bits SW Access HW Access Name VALUE [7:0] Bits SW Access HW Access Name VALUE [15:8] Bits SW Access HW Access Name VALUE [23:16] Bits SW Access HW Access...
  • Page 68 CM0_ROM_CID3 1.1.58 CM0_ROM_CID3 Address = 0xE00FFFFC CM0 CoreSight ROM Table Component ID #3 Address: 0xE00FFFFC Retention: Retained Bits SW Access HW Access Name VALUE [7:0] Bits SW Access HW Access Name VALUE [15:8] Bits SW Access HW Access Name VALUE [23:16] Bits SW Access HW Access...

  • Page 69: Cpuss Registers

    CPUSS Registers This section discusses the CPUSS registers of PSoC 4 device. It lists all the registers in mapping tables, in address order. CPUSS Register Mapping Details Register Address Description CPUSS_CONFIG 0x40100000 Configuration register CPUSS_SYSREQ 0x40100004 SYSCALL control register CPUSS_SYSARG 0x40100008 SYSARG control register CPUSS_PROTECTION...
  • Page 70 CPUSS_CONFIG 2.1.1 CPUSS_CONFIG Address = 0x40100000 Configuration register Address: 0x40100000 Retention: Retained Bits SW Access None HW Access None Name VECT_IN_R None [7:1] Bits SW Access None HW Access None Name None [15:8] Bits SW Access None HW Access None Name None [23:16] Bits...
  • Page 71 CPUSS_SYSREQ 2.1.2 CPUSS_SYSREQ Address = 0x40100004 SYSCALL control register Address: 0x40100004 Retention: Retained Bits SW Access HW Access Name SYSCALL_COMMAND [7:0] Bits SW Access HW Access Name SYSCALL_COMMAND [15:8] Bits SW Access None HW Access None Name None [23:16] Bits SW Access None HW Access...
  • Page 72 CPUSS_SYSREQ 2.1.2 CPUSS_SYSREQ (continued) PRIVILEGED Indicates whether the system is in privileged ('1') or user mode ('0'). Only CPU SW executing from ROM can set this field to '1' when ROM_ACCESS_EN is '1' (the CPU is executing a Sys- temCall NMI interrupt handler). Any other write to this field sets is to '0'. This field is used as the AHB-Lite hprot[1] signal to implement Cypress proprietary user/privileged modes.
  • Page 73 CPUSS_SYSARG 2.1.3 CPUSS_SYSARG Address = 0x40100008 SYSARG control register Address: 0x40100008 Retention: Retained Bits SW Access HW Access Name SYSCALL_ARG [7:0] Bits SW Access HW Access Name SYSCALL_ARG [15:8] Bits SW Access HW Access Name SYSCALL_ARG [23:16] Bits SW Access HW Access Name SYSCALL_ARG [31:24]...
  • Page 74 CPUSS_PROTECTION 2.1.4 CPUSS_PROTECTION Address = 0x4010000C Protection control register Address: 0x4010000C Retention: Retained Bits SW Access None HW Access None Name None [7:4] PROTECTION_MODE [3:0] Bits SW Access None HW Access None Name None [15:8] Bits SW Access None HW Access None Name None [23:16]...
  • Page 75 CPUSS_PRIV_ROM 2.1.5 CPUSS_PRIV_ROM Address = 0x40100010 ROM privilege register Address: 0x40100010 Retention: Retained Bits SW Access HW Access Name BROM_PROT_LIMIT [7:0] Bits SW Access None HW Access None Name None [15:8] Bits SW Access None HW Access None Name None [23:16] Bits SW Access None...
  • Page 76 CPUSS_PRIV_RAM 2.1.6 CPUSS_PRIV_RAM Address = 0x40100014 RAM privilege register Address: 0x40100014 Retention: Retained Bits SW Access HW Access Name RAM_PROT_LIMIT [7:0] Bits SW Access None HW Access None Name RAM_PRO None [15:9] T_LIMIT Bits SW Access None HW Access None Name None [23:16] Bits...
  • Page 77 CPUSS_PRIV_FLASH 2.1.7 CPUSS_PRIV_FLASH Address = 0x40100018 ROM privilege register Address: 0x40100018 Retention: Retained Bits SW Access HW Access Name FLASH_PROT_LIMIT [7:0] Bits SW Access None HW Access None Name None [15:11] FLASH_PROT_LIMIT [10:8] Bits SW Access None HW Access None Name None [23:16] Bits...
  • Page 78 CPUSS_WOUNDING 2.1.8 CPUSS_WOUNDING Address = 0x4010001C Wounding register Address: 0x4010001C Retention: Retained Bits SW Access None HW Access None Name None [7:0] Bits SW Access None HW Access None Name None [15:8] Bits SW Access None RW1S None RW1S HW Access None None Name...
  • Page 79 CPUSS_WOUNDING 2.1.8 CPUSS_WOUNDING (continued) 18 : 16 RAM_WOUND Indicates the amount of accessible RAM 0 memory capacitty in this part. The value in this field is effectively write-once (it is only possible to set bits, not clear them). The remainder portion of SRAM is not accessible and will return an AHB-Lite bus error.
  • Page 80 CPUSS_FLASH_CTL 2.1.9 CPUSS_FLASH_CTL Address = 0x40100030 FLASH control register Address: 0x40100030 Retention: Retained Bits SW Access None None HW Access None None Name None [7:5] PREF_EN None [3:2] FLASH_WS [1:0] Bits SW Access None HW Access None RW1C Name FLASH_IN- None [15:9] VALIDATE Bits...
  • Page 81 CPUSS_ROM_CTL 2.1.10 CPUSS_ROM_CTL Address = 0x40100034 ROM control register Address: 0x40100034 Retention: Retained Bits SW Access None HW Access None Name None [7:1] ROM_WS Bits SW Access None HW Access None Name None [15:8] Bits SW Access None HW Access None Name None [23:16]...

  • Page 82: Gpio Registers

    GPIO Registers This section discusses the GPIO registers of PSoC 4 device. It lists all the registers in mapping tables, in address order. GPIO Register Mapping Details Register Address Description GPIO_PRT0_DR 0x40040000 Port output data register GPIO_PRT0_PS 0x40040004 Port IO pad state register GPIO_PRT0_PC 0x40040008 Port configuration register...
  • Page 83 Register Address Description GPIO_PRT3_DR 0x40040300 Port output data register GPIO_PRT3_PS 0x40040304 Port IO pad state register GPIO_PRT3_PC 0x40040308 Port configuration register GPIO_PRT3_INTR_CFG 0x4004030C Port interrupt configuration register GPIO_PRT3_INTR 0x40040310 Port interrupt status register GPIO_PRT3_PC2 0x40040318 Port configuration register 2 GPIO_PRT3_DR_SET 0x40040340 Port output data set register.
  • Page 84 GPIO_PRT0_DR 3.1.1 GPIO_PRT0_DR Address = 0x40040000 Port output data register Address: 0x40040000 Retention: Retained Bits SW Access HW Access Name DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 Bits SW Access None HW Access None Name None [15:8] Bits SW Access None HW Access None...
  • Page 85 GPIO_PRT0_PS 3.1.2 GPIO_PRT0_PS Address = 0x40040004 Port IO pad state register Address: 0x40040004 Retention: Not Retained Bits SW Access HW Access Name DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 Bits SW Access None HW Access None Name None [15:9] FLT_DATA Bits SW Access...
  • Page 86 GPIO_PRT0_PS 3.1.2 GPIO_PRT0_PS (continued) DATA0 IO pad 0 state: 1: Logic high, if the pin voltage is above the input buffer threshold, logic high. 0: Logic low, if the pin voltage is below that threshold, logic low. If the drive mode for the pin is set to high Z Analog, the pin state will read 0 independent of the voltage on the pin.
  • Page 87 GPIO_PRT0_PC 3.1.3 GPIO_PRT0_PC Address = 0x40040008 Port configuration register Address: 0x40040008 Retention: Retained Bits SW Access HW Access Name DM2 [7:6] DM1 [5:3] DM0 [2:0] Bits SW Access HW Access Name DM4 [14:12] DM3 [11:9] Bits SW Access HW Access Name DM7 [23:21] DM6 [20:18]...
  • Page 88 GPIO_PRT0_PC 3.1.3 GPIO_PRT0_PC (continued) 14 : 12 The GPIO drive mode for IO pad 4. Default Value: 0 11 : 9 The GPIO drive mode for IO pad 3. Default Value: 0 8 : 6 The GPIO drive mode for IO pad 2. Default Value: 0 5 : 3 The GPIO drive mode for IO pad 1.
  • Page 89 GPIO_PRT0_INTR_CFG 3.1.4 GPIO_PRT0_INTR_CFG Address = 0x4004000C Port interrupt configuration register Address: 0x4004000C Retention: Retained Bits SW Access HW Access Name EDGE3_SEL [7:6] EDGE2_SEL [5:4] EDGE1_SEL [3:2] EDGE0_SEL [1:0] Bits SW Access HW Access Name EDGE7_SEL [15:14] EDGE6_SEL [13:12] EDGE5_SEL [11:10] EDGE4_SEL [9:8] Bits SW Access...
  • Page 90 GPIO_PRT0_INTR_CFG 3.1.4 GPIO_PRT0_INTR_CFG (continued) 0x3: BOTH : Both rising and falling edges 15 : 14 EDGE7_SEL Sets which edge will trigger an IRQ for IO pad 7. Default Value: 0 13 : 12 EDGE6_SEL Sets which edge will trigger an IRQ for IO pad 6. Default Value: 0 11 : 10 EDGE5_SEL...
  • Page 91 GPIO_PRT0_INTR 3.1.5 GPIO_PRT0_INTR Address = 0x40040010 Port interrupt status register Address: 0x40040010 Retention: Retained Bits SW Access RW1C RW1C RW1C RW1C RW1C RW1C RW1C RW1C HW Access Name DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 Bits SW Access None RW1C HW Access None...
  • Page 92 GPIO_PRT0_INTR 3.1.5 GPIO_PRT0_INTR (continued) DATA7 Interrupt pending on IO pad 7. Firmware writes 1 to clear the interrupt. Default Value: 0 DATA6 Interrupt pending on IO pad 6. Firmware writes 1 to clear the interrupt. Default Value: 0 DATA5 Interrupt pending on IO pad 5. Firmware writes 1 to clear the interrupt. Default Value: 0 DATA4 Interrupt pending on IO pad 4.
  • Page 93 GPIO_PRT0_PC2 3.1.6 GPIO_PRT0_PC2 Address = 0x40040018 Port configuration register 2 Address: 0x40040018 Retention: Retained Bits SW Access HW Access Name INP_DIS7 INP_DIS6 INP_DIS5 INP_DIS4 INP_DIS3 INP_DIS2 INP_DIS1 INP_DIS0 Bits SW Access None HW Access None Name None [15:8] Bits SW Access None HW Access None...
  • Page 94 GPIO_PRT0_PC2 3.1.6 GPIO_PRT0_PC2 (continued) INP_DIS0 Disables the input buffer for IO pad 0 independent of the port control drive mode (PC.DM). This bit should be set when analog signals are present on the pin and PC.DM != 0 is required to use the output driver.
  • Page 95 GPIO_PRT0_DR_SET 3.1.7 GPIO_PRT0_DR_SET Address = 0x40040040 Port output data set register Address: 0x40040040 Retention: Retained Bits SW Access HW Access Name DATA [7:0] Bits SW Access None HW Access None Name None [15:8] Bits SW Access None HW Access None Name None [23:16] Bits...
  • Page 96 GPIO_PRT0_DR_CLR 3.1.8 GPIO_PRT0_DR_CLR Address = 0x40040044 Port output data clear register Address: 0x40040044 Retention: Retained Bits SW Access HW Access Name DATA [7:0] Bits SW Access None HW Access None Name None [15:8] Bits SW Access None HW Access None Name None [23:16] Bits...
  • Page 97 GPIO_PRT0_DR_INV 3.1.9 GPIO_PRT0_DR_INV Address = 0x40040048 Port output data invert register Address: 0x40040048 Retention: Retained Bits SW Access HW Access Name DATA [7:0] Bits SW Access None HW Access None Name None [15:8] Bits SW Access None HW Access None Name None [23:16] Bits...
  • Page 98 GPIO_PRT2_DR 3.1.10 GPIO_PRT2_DR Address = 0x40040200 Port output data register Address: 0x40040200 Retention: Retained Bits SW Access None HW Access None Name None [7:1] DATA0 Bits SW Access None HW Access None Name None [15:8] Bits SW Access None HW Access None Name None [23:16]...
  • Page 99 GPIO_PRT2_PS 3.1.11 GPIO_PRT2_PS Address = 0x40040204 Port IO pad state register Address: 0x40040204 Retention: Not Retained Bits SW Access None HW Access None Name None [7:1] DATA0 Bits SW Access None HW Access None Name None [15:9] FLT_DATA Bits SW Access None HW Access None...
  • Page 100 GPIO_PRT2_PC 3.1.12 GPIO_PRT2_PC Address = 0x40040208 Port configuration register Address: 0x40040208 Retention: Retained Bits SW Access None HW Access None Name None [7:3] DM0 [2:0] Bits SW Access None HW Access None Name None [15:8] Bits SW Access None HW Access None Name None [23:16]...
  • Page 101 GPIO_PRT2_PC 3.1.12 GPIO_PRT2_PC (continued) 0x0: OFF : Mode 0 (analog mode): Output buffer off (high Z). Input buffer off. 0x1: INPUT : Mode 1: Output buffer off (high Z). Input buffer on. 0x2: 0_PU : Mode 2: Strong pull down ('0'), weak/resistive pull up (PU). Input buffer on. 0x3: PD_1 : Mode 3: Weak/resistive pull down (PD), strong pull up ('1').
  • Page 102 GPIO_PRT2_INTR_CFG 3.1.13 GPIO_PRT2_INTR_CFG Address = 0x4004020C Port interrupt configuration register Address: 0x4004020C Retention: Retained Bits SW Access None HW Access None Name None [7:2] EDGE0_SEL [1:0] Bits SW Access None HW Access None Name None [15:8] Bits SW Access None HW Access None Name...
  • Page 103 GPIO_PRT2_INTR_CFG 3.1.13 GPIO_PRT2_INTR_CFG (continued) 0x3: BOTH : Both rising and falling edges 1 : 0 EDGE0_SEL Sets which edge will trigger an IRQ for IO pad 0. Default Value: 0 0x0: DISABLE : Disabled 0x1: RISING : Rising edge 0x2: FALLING : Falling edge 0x3: BOTH : Both rising and falling edges...
  • Page 104 GPIO_PRT2_INTR 3.1.14 GPIO_PRT2_INTR Address = 0x40040210 Port interrupt status register Address: 0x40040210 Retention: Retained Bits SW Access None RW1C HW Access None Name None [7:1] DATA0 Bits SW Access None RW1C HW Access None Name None [15:9] FLT_DATA Bits SW Access None HW Access None...
  • Page 105 GPIO_PRT2_PC2 3.1.15 GPIO_PRT2_PC2 Address = 0x40040218 Port configuration register 2 Address: 0x40040218 Retention: Retained Bits SW Access None HW Access None Name None [7:1] INP_DIS0 Bits SW Access None HW Access None Name None [15:8] Bits SW Access None HW Access None Name None [23:16]...
  • Page 106 GPIO_PRT3_DR 3.1.16 GPIO_PRT3_DR Address = 0x40040300 Port output data register Address: 0x40040300 Retention: Retained Bits SW Access None HW Access None Name None [7:3] DATA2 DATA1 DATA0 Bits SW Access None HW Access None Name None [15:8] Bits SW Access None HW Access None...
  • Page 107 GPIO_PRT3_PS 3.1.17 GPIO_PRT3_PS Address = 0x40040304 Port IO pad state register Address: 0x40040304 Retention: Not Retained Bits SW Access None HW Access None Name None [7:3] DATA2 DATA1 DATA0 Bits SW Access None HW Access None Name None [15:9] FLT_DATA Bits SW Access None...
  • Page 108 GPIO_PRT3_PC 3.1.18 GPIO_PRT3_PC Address = 0x40040308 Port configuration register Address: 0x40040308 Retention: Retained Bits SW Access HW Access Name DM2 [7:6] DM1 [5:3] DM0 [2:0] Bits SW Access None HW Access None Name None [15:9] Bits SW Access None HW Access None Name None [23:16]...
  • Page 109 GPIO_PRT3_PC 3.1.18 GPIO_PRT3_PC (continued) 2 : 0 The GPIO drive mode for IO pad 0. Note: when initializing IO's that are connected to a live bus (such as I2C), make sure the HSIOM is properly configured (HSIOM_PRT_SELx) before turning the IO on here to avoid producing glitches on the bus.
  • Page 110 GPIO_PRT3_INTR_CFG 3.1.19 GPIO_PRT3_INTR_CFG Address = 0x4004030C Port interrupt configuration register Address: 0x4004030C Retention: Retained Bits SW Access None HW Access None Name None [7:6] EDGE2_SEL [5:4] EDGE1_SEL [3:2] EDGE0_SEL [1:0] Bits SW Access None HW Access None Name None [15:8] Bits SW Access None...
  • Page 111 GPIO_PRT3_INTR_CFG 3.1.19 GPIO_PRT3_INTR_CFG (continued) 0x3: BOTH : Both rising and falling edges 5 : 4 EDGE2_SEL Sets which edge will trigger an IRQ for IO pad 2. Default Value: 0 3 : 2 EDGE1_SEL Sets which edge will trigger an IRQ for IO pad 1. Default Value: 0 1 : 0 EDGE0_SEL...
  • Page 112 GPIO_PRT3_INTR 3.1.20 GPIO_PRT3_INTR Address = 0x40040310 Port interrupt status register Address: 0x40040310 Retention: Retained Bits SW Access None RW1C RW1C RW1C HW Access None Name None [7:3] DATA2 DATA1 DATA0 Bits SW Access None RW1C HW Access None Name None [15:9] FLT_DATA Bits SW Access...
  • Page 113 GPIO_PRT3_PC2 3.1.21 GPIO_PRT3_PC2 Address = 0x40040318 Port configuration register 2 Address: 0x40040318 Retention: Retained Bits SW Access None HW Access None Name None [7:3] INP_DIS2 INP_DIS1 INP_DIS0 Bits SW Access None HW Access None Name None [15:8] Bits SW Access None HW Access None...
  • Page 114 GPIO_INTR_CAUSE0 3.1.22 GPIO_INTR_CAUSE0 Address = 0x40041000 Interrupt port cause register Address: 0x40041000 Retention: Retained Bits SW Access None HW Access None Name None [7:4] PORT_INT [3:0] Bits SW Access None HW Access None Name None [15:8] Bits SW Access None HW Access None Name...

  • Page 115: Hsiom Registers

    HSIOM Registers This section discusses the HSIOM registers of PSoC 4 device. It lists all the registers in mapping tables, in address order. HSIOM Register Mapping Details Register Address Description HSIOM_PORT_SEL0 0x40020000 Port selection register HSIOM_PORT_SEL1 0x40020100 Port selection register. See HSIOM_PORT_SEL0 for the details of bit fields.
  • Page 116 HSIOM_PORT_SEL0 4.1.1 HSIOM_PORT_SEL0 Address = 0x40020000 Port selection register Address: 0x40020000 Retention: Retained Bits SW Access HW Access Name IO1_SEL [7:4] IO0_SEL [3:0] Bits SW Access HW Access Name IO3_SEL [15:12] IO2_SEL [11:8] Bits SW Access HW Access Name IO5_SEL [23:20] IO4_SEL [19:16] Bits SW Access...
  • Page 117 HSIOM_PORT_SEL0 4.1.1 HSIOM_PORT_SEL0 (continued) 0x0: GPIO : SW controlled GPIO. 0x1: GPIO_DSI : SW controlled "out", DSI controlled "oe_n". 0x2: DSI_DSI : DSI controlled "out" and "oe_n". 0x3: DSI_GPIO : DSI controlled "out", SW controlled "oe_n". 0x4: CSD_SENSE : CSD sense connection (analog mode) 0x5: CSD_SHIELD : CSD shield connection (analog mode) 0x6: AMUXA :...
  • Page 118 HSIOM_PORT_SEL0 4.1.1 HSIOM_PORT_SEL0 (continued) 0xc: LCD_COM : LCD common connection. This mode provides DeepSleep functionality (provided that the LCD block is enabled and properly configured). 0xd: LCD_SEG : LCD segment connection. This mode provides DeepSleep functionality (provided that the LCD block is enabled and properly configured).
  • Page 119 HSIOM_PORT_SEL2 4.1.2 HSIOM_PORT_SEL2 Address = 0x40020200 Port selection register Address: 0x40020200 Retention: Retained Bits SW Access None HW Access None Name None [7:4] IO0_SEL [3:0] Bits SW Access None HW Access None Name None [15:8] Bits SW Access None HW Access None Name None [23:16]...
  • Page 120 HSIOM_PORT_SEL2 4.1.2 HSIOM_PORT_SEL2 (continued) 0x4: CSD_SENSE : CSD sense connection (analog mode) 0x5: CSD_SHIELD : CSD shield connection (analog mode) 0x6: AMUXA : AMUXBUS A connection. 0x7: AMUXB : AMUXBUS B connection. This mode is also used for CSD GPIO charging. When CSD GPIO charging is enabled in CSD_CONTROL, "oe_n"...
  • Page 121 HSIOM_PORT_SEL2 4.1.2 HSIOM_PORT_SEL2 (continued) 0xd: DS_1 : Chip specific DeepSleep source 1 connection. 0xe: DS_2 : Chip specific DeepSleep source 2 connection. 0xf: DS_3 : Chip specific DeepSleep source 3 connection. PSoC 4 Registers TRM, Document Number: 001-90002 Rev. *E...
  • Page 122 HSIOM_PORT_SEL3 4.1.3 HSIOM_PORT_SEL3 Address = 0x40020300 Port selection register Address: 0x40020300 Retention: Retained Bits SW Access HW Access Name IO1_SEL [7:4] IO0_SEL [3:0] Bits SW Access None HW Access None Name None [15:12] IO2_SEL [11:8] Bits SW Access None HW Access None Name None [23:16]...
  • Page 123 HSIOM_PORT_SEL3 4.1.3 HSIOM_PORT_SEL3 (continued) 0x3: DSI_GPIO : DSI controlled "out", SW controlled "oe_n". 0x4: CSD_SENSE : CSD sense connection (analog mode) 0x5: CSD_SHIELD : CSD shield connection (analog mode) 0x6: AMUXA : AMUXBUS A connection. 0x7: AMUXB : AMUXBUS B connection. This mode is also used for CSD GPIO charging. When CSD GPIO charging is enabled in CSD_CONTROL, "oe_n"...
  • Page 124 HSIOM_PORT_SEL3 4.1.3 HSIOM_PORT_SEL3 (continued) 0xc: DS_0 : Chip specific DeepSleep source 0 connection. 0xd: DS_1 : Chip specific DeepSleep source 1 connection. 0xe: DS_2 : Chip specific DeepSleep source 2 connection. 0xf: DS_3 : Chip specific DeepSleep source 3 connection. PSoC 4 Registers TRM, Document Number: 001-90002 Rev.
  • Page 125 HSIOM_PUMP_CTL 4.1.4 HSIOM_PUMP_CTL Address = 0x40022000 Pump control Address: 0x40022000 Retention: Retained Bits SW Access None HW Access None Name CLOCK_- None [7:1] Bits SW Access None HW Access None Name None [15:8] Bits SW Access None HW Access None Name None [23:16] Bits...

  • Page 126: Peri Registers

    PERI Registers This section discusses the PERI registers of PSoC 4 device. It lists all the registers in mapping tables, in address order. PERI Register Mapping Details Register Address Description PERI_DIV_CMD 0x40010000 Divider command register PERI_PCLK_CTL0 0x40010100 Programmable clock control register PERI_PCLK_CTL1 0x40010104 Programmable clock control register.
  • Page 127 PERI_DIV_CMD 5.1.1 PERI_DIV_CMD Address = 0x40010000 Divider command register Address: 0x40010000 Retention: Not Retained Bits SW Access HW Access Name SEL_TYPE [7:6] SEL_DIV [5:0] Bits SW Access HW Access Name PA_SEL_TYPE [15:14] PA_SEL_DIV [13:8] Bits SW Access None HW Access None Name None [23:16]...
  • Page 128 PERI_DIV_CMD 5.1.1 PERI_DIV_CMD (continued) DISABLE Clock divider disable command (mutually exlusive with ENABLE). SW sets this field to '1' and HW sets this field to '0'. The SEL_DIV and SEL_TYPE fields specify which divider is to be disabled. The HW sets the DISABLE field to '0' immediately and the HW sets the DIV_XXX_CTL.EN field of the divider to '0' immediately.
  • Page 129 PERI_PCLK_CTL0 5.1.2 PERI_PCLK_CTL0 Address = 0x40010100 Programmable clock control register Address: 0x40010100 Retention: Retained Bits SW Access None HW Access None Name SEL_TYPE [7:6] None [5:2] SEL_DIV [1:0] Bits SW Access None HW Access None Name None [15:8] Bits SW Access None HW Access None...
  • Page 130 PERI_DIV_16_CTL0 5.1.3 PERI_DIV_16_CTL0 Address = 0x40010300 Divider control register (for 16.0 divider) Address: 0x40010300 Retention: Retained Bits SW Access None HW Access None Name None [7:1] Bits SW Access HW Access Name INT16_DIV [15:8] Bits SW Access HW Access Name INT16_DIV [23:16] Bits SW Access...

  • Page 131: Scb Registers

    SCB Registers This section discusses the SCB registers of PSoC 4 device. It lists all the registers in mapping tables, in address order. SCB Register Mapping Details Register Address Description SCB_CTRL 0x40060000 Generic control register. SCB_STATUS 0x40060004 Generic status register. SCB_I2C_CTRL 0x40060060 I2C control register.
  • Page 132 Register Address Description SCB_EZ_DATA10 0x40060428 Memory buffer registers. See SCB_EZ_DATA0 for the details of bit fields. SCB_EZ_DATA11 0x4006042C Memory buffer registers. See SCB_EZ_DATA0 for the details of bit fields. SCB_EZ_DATA12 0x40060430 Memory buffer registers. See SCB_EZ_DATA0 for the details of bit fields. SCB_EZ_DATA13 0x40060434 Memory buffer registers.
  • Page 133 SCB_CTRL 6.1.1 SCB_CTRL Address = 0x40060000 Generic control register. Address: 0x40060000 Retention: Retained Bits SW Access None HW Access None Name None [7:4] OVS [3:0] Bits SW Access None HW Access None Name BYTE_- EC_OP_- EC_AM_- None [15:12] EZ_MODE MODE MODE MODE Bits...
  • Page 134 SCB_CTRL 6.1.1 SCB_CTRL (continued) 0x0: I2C : Inter-Integrated Circuits (I2C) mode. 0x1: SPI : Serial Peripheral Interface (SPI) mode. 0x2: UART : Universal Asynchronous Receiver/Transmitter (UART) mode. BLOCK Only used in externally clocked mode. If the externally clocked logic and the MMIO SW accesses to EZ memory coincide/collide, this bit determines whether a SW access should block and result in bus wait states ('BLOCK is 1') or not (BLOCK is '0').
  • Page 135 SCB_CTRL 6.1.1 SCB_CTRL (continued) EC_OP_MODE Internally clocked mode ('0') or externally clocked mode ('1') operation. In internally clocked mode, the serial interface protocols run off the peripheral clock. In externally clocked mode, the serial interface protocols run off the clock as provided by the serial interface. Externally clocked operation mode is only used for synchronous serial interface protocols (SPI and I2C) in slave mode AND EZ mode.
  • Page 136 SCB_CTRL 6.1.1 SCB_CTRL (continued) 3 : 0 Serial interface bit period oversampling factor expressed in lP clock cycles. Used for SPI and UART functionality. OVS + 1 IP clock cycles constitute a single serial interface clock/bit cycle. The IP clock is provided by the programmable clock IP. This field is NOT used in externally clocked mode.
  • Page 137 SCB_STATUS 6.1.2 SCB_STATUS Address = 0x40060004 Generic status register. Address: 0x40060004 Retention: Not Retained Bits SW Access None HW Access None Name None [7:1] EC_BUSY Bits SW Access None HW Access None Name None [15:8] Bits SW Access None HW Access None Name None [23:16]...
  • Page 138 SCB_I2C_CTRL 6.1.3 SCB_I2C_CTRL Address = 0x40060060 I2C control register. Address: 0x40060060 Retention: Retained Bits SW Access HW Access Name LOW_PHASE_OVS [7:4] HIGH_PHASE_OVS [3:0] Bits SW Access None HW Access None M_NOT_RE Name S_NOT_RE S_NOT_RE S_GENER- ADY_- S_READY_ S_READY_ ADY_- M_READY_ ADY_AD- AL_IGNOR None...
  • Page 139 SCB_I2C_CTRL 6.1.3 SCB_I2C_CTRL (continued) S_NOT_READY_- For internally clocked logic only. Only used when: DATA_NACK - non EZ mode. Functionality is as follows: - 1: a received data element byte the slave is immediately NACK'd when the receiver FIFO is full. - 0: clock stretching is performed (till the receiver FIFO is no longer full).
  • Page 140 SCB_I2C_CTRL 6.1.3 SCB_I2C_CTRL (continued) 7 : 4 LOW_PHASE_OVS Serial I2C interface low phase oversampling factor. LOW_PHASE_OVS + 1 peripheral clock pe- riods constitute the low phase of a bit period. The valid range is [7, 15] with input signal median filtering and [6, 15] without input signal median filtering.
  • Page 141 SCB_I2C_STATUS 6.1.4 SCB_I2C_STATUS Address = 0x40060064 I2C status register. Address: 0x40060064 Retention: Not Retained Bits SW Access None None HW Access None None Name I2C_EC_BU None [7:6] M_READ S_READ None [3:2] BUS_BUSY Bits SW Access HW Access Name CURR_EZ_ADDR [15:8] Bits SW Access HW Access...
  • Page 142 SCB_I2C_STATUS 6.1.4 SCB_I2C_STATUS (continued) I2C_EC_BUSY Inidicates whether the externally clocked logic is potentially accessing the EZ memory and/or up- dating BASE_ADDR or CURR_ADDR (this is only possible in EZ mode). This bit can be used by SW to determine whether BASE_ADDR and CURR_ADDR are reliable. Default Value: Undefined BUS_BUSY I2C bus is busy.
  • Page 143 SCB_I2C_M_CMD 6.1.5 SCB_I2C_M_CMD Address = 0x40060068 I2C master command register. Address: 0x40060068 Retention: Not Retained Bits SW Access None HW Access None RW1C RW1C RW1C RW1C RW1C Name M_START_ None [7:5] M_STOP M_NACK M_ACK M_START ON_IDLE Bits SW Access None HW Access None Name...
  • Page 144 SCB_I2C_M_CMD 6.1.5 SCB_I2C_M_CMD (continued) M_START_ON_IDLE When '1', transmit a START as soon as the bus is idle (I2C_STATUS.BUS_BUSY is '0', note that BUSY has a default value of '0'). For bus idle detection the hardware relies on STOP detection. As a result, bus idle detection is only functional after at least one I2C bus transfer has been de- tected on the bus (default/reset value of BUSY is '0') .
  • Page 145 SCB_I2C_S_CMD 6.1.6 SCB_I2C_S_CMD Address = 0x4006006C I2C slave command register. Address: 0x4006006C Retention: Not Retained Bits SW Access None HW Access None RW1C RW1C Name None [7:2] S_NACK S_ACK Bits SW Access None HW Access None Name None [15:8] Bits SW Access None HW Access...
  • Page 146 SCB_I2C_CFG 6.1.7 SCB_I2C_CFG Address = 0x40060070 I2C configuration register. Address: 0x40060070 Retention: Retained Bits SW Access None None HW Access None None Name SDA_IN_- None [7:5] None [3:2] SDA_IN_FILT_TRIM [1:0] FILT_SEL Bits SW Access None None HW Access None None Name SCL_IN_- None [15:13]...
  • Page 147 SCB_I2C_CFG 6.1.7 SCB_I2C_CFG (continued) SCL_IN_FILT_SEL Selection of "i2c_scl_in" filter delay: '0': 0 ns. '1: 50 ns (filter enabled). Default Value: 1 9 : 8 SCL_IN_FILT_TRIM Trim bits for "i2c_scl_in" 50 ns filter. Default Value: 0 SDA_IN_FILT_SEL Selection of "i2c_sda_in" filter delay: '0': 0 ns.
  • Page 148 SCB_TX_CTRL 6.1.8 SCB_TX_CTRL Address = 0x40060200 Transmitter control register. Address: 0x40060200 Retention: Retained Bits SW Access None HW Access None Name None [7:4] DATA_WIDTH [3:0] Bits SW Access None HW Access None Name MSB_- None [15:9] FIRST Bits SW Access None HW Access None...
  • Page 149 SCB_TX_FIFO_CTRL 6.1.9 SCB_TX_FIFO_CTRL Address = 0x40060204 Transmitter FIFO control register. Address: 0x40060204 Retention: Retained Bits SW Access None HW Access None Name None [7:4] TRIGGER_LEVEL [3:0] Bits SW Access None HW Access None Name None [15:8] Bits SW Access None HW Access None Name...
  • Page 150 SCB_TX_FIFO_STATUS 6.1.10 SCB_TX_FIFO_STATUS Address = 0x40060208 Transmitter FIFO status register. Address: 0x40060208 Retention: Not Retained Bits SW Access None HW Access None Name None [7:5] USED [4:0] Bits SW Access None HW Access None Name SR_VALID None [14:8] Bits SW Access None HW Access None...
  • Page 151 SCB_TX_FIFO_WR 6.1.11 SCB_TX_FIFO_WR Address = 0x40060240 Transmitter FIFO write register. Address: 0x40060240 Retention: Not Retained Bits SW Access HW Access Name DATA [7:0] Bits SW Access HW Access Name DATA [15:8] Bits SW Access None HW Access None Name None [23:16] Bits SW Access None...
  • Page 152 SCB_RX_CTRL 6.1.12 SCB_RX_CTRL Address = 0x40060300 Receiver control register. Address: 0x40060300 Retention: Retained Bits SW Access None HW Access None Name None [7:4] DATA_WIDTH [3:0] Bits SW Access None HW Access None Name MSB_- None [15:10] MEDIAN FIRST Bits SW Access None HW Access None...
  • Page 153 SCB_RX_FIFO_CTRL 6.1.13 SCB_RX_FIFO_CTRL Address = 0x40060304 Receiver FIFO control register. Address: 0x40060304 Retention: Retained Bits SW Access None HW Access None Name None [7:4] TRIGGER_LEVEL [3:0] Bits SW Access None HW Access None Name None [15:8] Bits SW Access None HW Access None Name...
  • Page 154 SCB_RX_FIFO_STATUS 6.1.14 SCB_RX_FIFO_STATUS Address = 0x40060308 Receiver FIFO status register. Address: 0x40060308 Retention: Not Retained Bits SW Access None HW Access None Name None [7:5] USED [4:0] Bits SW Access None HW Access None Name SR_VALID None [14:8] Bits SW Access None HW Access None...
  • Page 155 SCB_RX_MATCH 6.1.15 SCB_RX_MATCH Address = 0x40060310 Slave address and mask register. Address: 0x40060310 Retention: Retained Bits SW Access HW Access Name ADDR [7:0] Bits SW Access None HW Access None Name None [15:8] Bits SW Access HW Access Name MASK [23:16] Bits SW Access None...
  • Page 156 SCB_RX_FIFO_RD 6.1.16 SCB_RX_FIFO_RD Address = 0x40060340 Receiver FIFO read register. Address: 0x40060340 Retention: Not Retained Bits SW Access HW Access Name DATA [7:0] Bits SW Access HW Access Name DATA [15:8] Bits SW Access None HW Access None Name None [23:16] Bits SW Access None...
  • Page 157 SCB_RX_FIFO_RD_SILENT 6.1.17 SCB_RX_FIFO_RD_SILENT Address = 0x40060344 Receiver FIFO read register. Address: 0x40060344 Retention: Not Retained Bits SW Access HW Access Name DATA [7:0] Bits SW Access HW Access Name DATA [15:8] Bits SW Access None HW Access None Name None [23:16] Bits SW Access None...
  • Page 158 SCB_EZ_DATA0 6.1.18 SCB_EZ_DATA0 Address = 0x40060400 Memory buffer registers. Address: 0x40060400 Retention: Retained Bits SW Access HW Access Name EZ_DATA [7:0] Bits SW Access None HW Access None Name None [15:8] Bits SW Access None HW Access None Name None [23:16] Bits SW Access None...
  • Page 159 SCB_INTR_CAUSE 6.1.19 SCB_INTR_CAUSE Address = 0x40060E00 Active clocked interrupt signal register Address: 0x40060E00 Retention: Retained Bits SW Access None HW Access None Name None [7:5] I2C_EC Bits SW Access None HW Access None Name None [15:8] Bits SW Access None HW Access None Name...
  • Page 160 SCB_INTR_I2C_EC 6.1.20 SCB_INTR_I2C_EC Address = 0x40060E80 Externally clocked I2C interrupt request register Address: 0x40060E80 Retention: Retained Bits SW Access None RW1C RW1C RW1C RW1C HW Access None Name EZ_READ_ EZ_WRITE None [7:4] EZ_STOP WAKE_UP STOP _STOP Bits SW Access None HW Access None Name...
  • Page 161 SCB_INTR_I2C_EC 6.1.20 SCB_INTR_I2C_EC (continued) WAKE_UP Wake up request. Active on incoming slave request (with address match). Only used when EC_AM is '1'. Default Value: 0 PSoC 4 Registers TRM, Document Number: 001-90002 Rev. *E...
  • Page 162 SCB_INTR_I2C_EC_MASK 6.1.21 SCB_INTR_I2C_EC_MASK Address = 0x40060E88 Externally clocked I2C interrupt mask register Address: 0x40060E88 Retention: Retained Bits SW Access None HW Access None Name EZ_READ_ EZ_WRITE None [7:4] EZ_STOP WAKE_UP STOP _STOP Bits SW Access None HW Access None Name None [15:8] Bits SW Access...
  • Page 163 SCB_INTR_I2C_EC_MASKED 6.1.22 SCB_INTR_I2C_EC_MASKED Address = 0x40060E8C Externally clocked I2C interrupt masked register Address: 0x40060E8C Retention: Retained Bits SW Access None HW Access None Name EZ_READ_ EZ_WRITE None [7:4] EZ_STOP WAKE_UP STOP _STOP Bits SW Access None HW Access None Name None [15:8] Bits SW Access...
  • Page 164 SCB_INTR_M 6.1.23 SCB_INTR_M Address = 0x40060F00 Master interrupt request register. Address: 0x40060F00 Retention: Not Retained Bits SW Access None RW1C None RW1C RW1C RW1C HW Access None RW1S None RW1S RW1S RW1S Name I2C_AR- None [7:5] I2C_STOP None I2C_ACK I2C_NACK B_LOST Bits SW Access...
  • Page 165 SCB_INTR_M_SET 6.1.24 SCB_INTR_M_SET Address = 0x40060F04 Master interrupt set request register Address: 0x40060F04 Retention: Not Retained Bits SW Access None RW1S None RW1S RW1S RW1S HW Access None None Name I2C_AR- None [7:5] I2C_STOP None I2C_ACK I2C_NACK B_LOST Bits SW Access None RW1S HW Access...
  • Page 166 SCB_INTR_M_MASK 6.1.25 SCB_INTR_M_MASK Address = 0x40060F08 Master interrupt mask register. Address: 0x40060F08 Retention: Retained Bits SW Access None None HW Access None None Name I2C_AR- None [7:5] I2C_STOP None I2C_ACK I2C_NACK B_LOST Bits SW Access None HW Access None Name I2C_BUS_E None [15:9] RROR...
  • Page 167 SCB_INTR_M_MASKED 6.1.26 SCB_INTR_M_MASKED Address = 0x40060F0C Master interrupt masked request register Address: 0x40060F0C Retention: Not Retained Bits SW Access None None HW Access None None Name I2C_AR- None [7:5] I2C_STOP None I2C_ACK I2C_NACK B_LOST Bits SW Access None HW Access None Name I2C_BUS_E...
  • Page 168 SCB_INTR_S 6.1.27 SCB_INTR_S Address = 0x40060F40 Slave interrupt request register. Address: 0x40060F40 Retention: Not Retained Bits SW Access RW1C RW1C RW1C RW1C RW1C RW1C RW1C RW1C HW Access RW1S RW1S RW1S RW1S RW1S RW1S RW1S RW1S Name I2C_GEN- I2C_AD- I2C_WRITE I2C_AR- I2C_START I2C_STOP...
  • Page 169 SCB_INTR_S 6.1.27 SCB_INTR_S (continued) I2C_START I2C slave START received. Set to '1', when START or REPEATED START event is detected. In the case of externally clocked address matching (CTRL.EC_AM_MODE is '1') AND clock stretching is performed (till the internally clocked logic takes over) (I2C_C- TRL.S_NOT_READY_ADDR_NACK is '0'), this field is NOT set.
  • Page 170 SCB_INTR_S_SET 6.1.28 SCB_INTR_S_SET Address = 0x40060F44 Slave interrupt set request register. Address: 0x40060F44 Retention: Not Retained Bits SW Access RW1S RW1S RW1S RW1S RW1S RW1S RW1S RW1S HW Access Name I2C_GEN- I2C_AD- I2C_WRITE I2C_AR- I2C_START I2C_STOP I2C_ACK I2C_NACK ERAL DR_MATCH _STOP B_LOST Bits...
  • Page 171 SCB_INTR_S_SET 6.1.28 SCB_INTR_S_SET (continued) I2C_NACK Write with '1' to set corresponding bit in interrupt request register. Default Value: 0 I2C_ARB_LOST Write with '1' to set corresponding bit in interrupt request register. Default Value: 0 PSoC 4 Registers TRM, Document Number: 001-90002 Rev. *E...
  • Page 172 SCB_INTR_S_MASK 6.1.29 SCB_INTR_S_MASK Address = 0x40060F48 Slave interrupt mask register. Address: 0x40060F48 Retention: Retained Bits SW Access HW Access Name I2C_GEN- I2C_AD- I2C_WRITE I2C_AR- I2C_START I2C_STOP I2C_ACK I2C_NACK ERAL DR_MATCH _STOP B_LOST Bits SW Access None HW Access None Name I2C_BUS_E None [15:9] RROR...
  • Page 173 SCB_INTR_S_MASK 6.1.29 SCB_INTR_S_MASK (continued) I2C_NACK Mask bit for corresponding bit in interrupt request register. Default Value: 0 I2C_ARB_LOST Mask bit for corresponding bit in interrupt request register. Default Value: 0 PSoC 4 Registers TRM, Document Number: 001-90002 Rev. *E...
  • Page 174 SCB_INTR_S_MASKED 6.1.30 SCB_INTR_S_MASKED Address = 0x40060F4C Slave interrupt masked request register Address: 0x40060F4C Retention: Not Retained Bits SW Access HW Access Name I2C_GEN- I2C_AD- I2C_WRITE I2C_AR- I2C_START I2C_STOP I2C_ACK I2C_NACK ERAL DR_MATCH _STOP B_LOST Bits SW Access None HW Access None Name I2C_BUS_E...
  • Page 175 SCB_INTR_S_MASKED 6.1.30 SCB_INTR_S_MASKED (continued) I2C_NACK Logical and of corresponding request and mask bits. Default Value: 0 I2C_ARB_LOST Logical and of corresponding request and mask bits. Default Value: 0 PSoC 4 Registers TRM, Document Number: 001-90002 Rev. *E...
  • Page 176 SCB_INTR_TX 6.1.31 SCB_INTR_TX Address = 0x40060F80 Transmitter interrupt request register. Address: 0x40060F80 Retention: Not Retained Bits SW Access RW1C RW1C RW1C RW1C None RW1C RW1C HW Access RW1S RW1S RW1S RW1S None RW1S RW1S Name UNDER- OVER- BLOCKED EMPTY None [3:2] NOT_FULL TRIGGER FLOW...
  • Page 177 SCB_INTR_TX 6.1.31 SCB_INTR_TX (continued) NOT_FULL TX FIFO is not full. Dependent on CTRL.BYTE_MODE: BYTE_MODE is '0': # entries != FF_DATA_NR/2. BYTE_MODE is '1': # entries != FF_DATA_NR. Only used in FIFO mode. Default Value: 0 TRIGGER Less entries in the TX FIFO than the value specified by TX_FIFO_CTRL. Only used in FIFO mode.
  • Page 178 SCB_INTR_TX_SET 6.1.32 SCB_INTR_TX_SET Address = 0x40060F84 Transmitter interrupt set request register Address: 0x40060F84 Retention: Not Retained Bits SW Access RW1S RW1S RW1S RW1S None RW1S RW1S HW Access None Name UNDER- OVER- BLOCKED EMPTY None [3:2] NOT_FULL TRIGGER FLOW FLOW Bits SW Access None...
  • Page 179 SCB_INTR_TX_MASK 6.1.33 SCB_INTR_TX_MASK Address = 0x40060F88 Transmitter interrupt mask register. Address: 0x40060F88 Retention: Retained Bits SW Access None HW Access None Name UNDER- OVER- BLOCKED EMPTY None [3:2] NOT_FULL TRIGGER FLOW FLOW Bits SW Access None HW Access None Name None [15:8] Bits SW Access...
  • Page 180 SCB_INTR_TX_MASKED 6.1.34 SCB_INTR_TX_MASKED Address = 0x40060F8C Transmitter interrupt masked request register Address: 0x40060F8C Retention: Not Retained Bits SW Access None HW Access None Name UNDER- OVER- BLOCKED EMPTY None [3:2] NOT_FULL TRIGGER FLOW FLOW Bits SW Access None HW Access None Name None [15:8]...
  • Page 181 SCB_INTR_RX 6.1.35 SCB_INTR_RX Address = 0x40060FC0 Receiver interrupt request register. Address: 0x40060FC0 Retention: Not Retained Bits SW Access RW1C RW1C RW1C None RW1C RW1C None RW1C HW Access RW1S RW1S RW1S None RW1S RW1S None RW1S Name UNDER- OVER- NOT_EMP- BLOCKED None FULL...
  • Page 182 SCB_INTR_RX 6.1.35 SCB_INTR_RX (continued) FULL RX FIFO is full. Note that received data frames are lost when the RX FIFO is full. Dependent on CTRL.BYTE_MODET: BYTE_MODE is '0': # entries == FF_DATA_NR/2. BYTE_MODE is '1': # entries == FF_DATA_NR. Only used in FIFO mode. Default Value: 0 NOT_EMPTY RX FIFO is not empty.
  • Page 183 SCB_INTR_RX_SET 6.1.36 SCB_INTR_RX_SET Address = 0x40060FC4 Receiver interrupt set request register. Address: 0x40060FC4 Retention: Not Retained Bits SW Access RW1S RW1S RW1S None RW1S RW1S None RW1S HW Access None None Name UNDER- OVER- NOT_EMP- BLOCKED None FULL None TRIGGER FLOW FLOW Bits...
  • Page 184 SCB_INTR_RX_MASK 6.1.37 SCB_INTR_RX_MASK Address = 0x40060FC8 Receiver interrupt mask register. Address: 0x40060FC8 Retention: Retained Bits SW Access None None HW Access None None Name UNDER- OVER- NOT_EMP- BLOCKED None FULL None TRIGGER FLOW FLOW Bits SW Access None HW Access None Name None [15:8]...
  • Page 185 SCB_INTR_RX_MASKED 6.1.38 SCB_INTR_RX_MASKED Address = 0x40060FCC Receiver interrupt masked request register Address: 0x40060FCC Retention: Not Retained Bits SW Access None None HW Access None None Name UNDER- OVER- NOT_EMP- BLOCKED None FULL None TRIGGER FLOW FLOW Bits SW Access None HW Access None Name...

  • Page 186: Sflash Registers

    SFLASH Registers This section discusses the SFLASH registers of PSoC 4 device. It lists all the registers in mapping tables, in address order. SFLASH Register Mapping Details Register Address Description SFLASH_SILICON_ID 0x0FFFF144 Silicon ID SFLASH_HIB_KEY_DELAY 0x0FFFF150 Hibernate wakeup value for PWR_KEY_DELAY SFLASH_DPSLP_KEY_DELAY 0x0FFFF152 DeepSleep wakeup value for PWR_KEY_DELAY...
  • Page 187 Register Address Description IMO TempCo Trim Register (SRSS-Lite). See SFLASH_IMO_TCTRIM_LT0 for the details of bit SFLASH_IMO_TCTRIM_LT11 0x0FFFF1D7 fields. IMO TempCo Trim Register (SRSS-Lite). See SFLASH_IMO_TCTRIM_LT0 for the details of bit SFLASH_IMO_TCTRIM_LT12 0x0FFFF1D8 fields. IMO TempCo Trim Register (SRSS-Lite). See SFLASH_IMO_TCTRIM_LT0 for the details of bit SFLASH_IMO_TCTRIM_LT13 0x0FFFF1D9...
  • Page 188 Register Address Description IMO Frequency Trim Register (SRSS-Lite). See SFLASH_IMO_TRIM_LT0 for the details of bit SFLASH_IMO_TRIM_LT15 0x0FFFF1F4 fields. IMO Frequency Trim Register (SRSS-Lite). See SFLASH_IMO_TRIM_LT0 for the details of bit SFLASH_IMO_TRIM_LT16 0x0FFFF1F5 fields. IMO Frequency Trim Register (SRSS-Lite). See SFLASH_IMO_TRIM_LT0 for the details of bit SFLASH_IMO_TRIM_LT17 0x0FFFF1F6...
  • Page 189 SFLASH_SILICON_ID 7.1.1 SFLASH_SILICON_ID Address = 0x0FFFF144 Silicon ID Address: 0x0FFFF144 Retention: Retained Bits SW Access HW Access Name ID [7:0] Bits SW Access HW Access Name ID [15:8] Bits SW Access None HW Access None Name None [23:16] Bits SW Access None HW Access None...
  • Page 190 SFLASH_HIB_KEY_DELAY 7.1.2 SFLASH_HIB_KEY_DELAY Address = 0x0FFFF150 Hibernate wakeup value for PWR_KEY_DELAY Address: 0x0FFFF150 Retention: Retained Bits SW Access HW Access Name WAKEUP_HOLDOFF [7:0] Bits SW Access None HW Access None Name None [15:10] WAKEUP_HOLDOFF [9:8] Bits Name Description 9 : 0 WAKEUP_HOLDOFF Delay (in 12MHz IMO clock cycles) to wait for references to settle on wakeup from hibernate/ deepsleep.
  • Page 191 SFLASH_DPSLP_KEY_DELAY 7.1.3 SFLASH_DPSLP_KEY_DELAY Address = 0x0FFFF152 DeepSleep wakeup value for PWR_KEY_DELAY Address: 0x0FFFF152 Retention: Retained Bits SW Access HW Access Name WAKEUP_HOLDOFF [7:0] Bits SW Access None HW Access None Name None [15:10] WAKEUP_HOLDOFF [9:8] Bits Name Description 9 : 0 WAKEUP_HOLDOFF Delay (in 12MHz IMO clock cycles) to wait for references to settle on wakeup from hibernate/ deepsleep.
  • Page 192 SFLASH_SWD_CONFIG 7.1.4 SFLASH_SWD_CONFIG Address = 0x0FFFF154 SWD pinout selector (not present in TSG4/TSG5-M) Address: 0x0FFFF154 Retention: Retained Bits SW Access None HW Access None Name SWD_SE- None [7:1] LECT Bits Name Description SWD_SELECT 0: Use Primary SWD location 1: Use Alternate SWD location Default Value: X PSoC 4 Registers TRM, Document Number: 001-90002 Rev.
  • Page 193 SFLASH_SWD_LISTEN 7.1.5 SFLASH_SWD_LISTEN Address = 0x0FFFF158 Listen Window Length Address: 0x0FFFF158 Retention: Retained Bits SW Access HW Access Name CYCLES [7:0] Bits SW Access HW Access Name CYCLES [15:8] Bits SW Access HW Access Name CYCLES [23:16] Bits SW Access HW Access Name CYCLES [31:24]...
  • Page 194 SFLASH_FLASH_START 7.1.6 SFLASH_FLASH_START Address = 0x0FFFF15C Flash Image Start Address Address: 0x0FFFF15C Retention: Retained Bits SW Access HW Access Name ADDRESS [7:0] Bits SW Access HW Access Name ADDRESS [15:8] Bits SW Access HW Access Name ADDRESS [23:16] Bits SW Access HW Access Name ADDRESS [31:24]...
  • Page 195 SFLASH_CSD_TRIM1_HVIDAC 7.1.7 SFLASH_CSD_TRIM1_HVIDAC Address = 0x0FFFF160 CSD Trim Data for HVIDAC operation Address: 0x0FFFF160 Retention: Retained Bits SW Access HW Access Name TRIM8 [7:0] Bits Name Description 7 : 0 TRIM8 Trim data Default Value: X PSoC 4 Registers TRM, Document Number: 001-90002 Rev. *E...
  • Page 196 SFLASH_CSD_TRIM2_HVIDAC 7.1.8 SFLASH_CSD_TRIM2_HVIDAC Address = 0x0FFFF161 CSD Trim Data for HVIDAC operation Address: 0x0FFFF161 Retention: Retained Bits SW Access HW Access Name TRIM8 [7:0] Bits Name Description 7 : 0 TRIM8 Trim data Default Value: X PSoC 4 Registers TRM, Document Number: 001-90002 Rev. *E...
  • Page 197 SFLASH_CSD_TRIM1_CSD 7.1.9 SFLASH_CSD_TRIM1_CSD Address = 0x0FFFF162 CSD Trim Data for (normal) CSD operation Address: 0x0FFFF162 Retention: Retained Bits SW Access HW Access Name TRIM8 [7:0] Bits Name Description 7 : 0 TRIM8 Trim data Default Value: X PSoC 4 Registers TRM, Document Number: 001-90002 Rev. *E...
  • Page 198 SFLASH_CSD_TRIM2_CSD 7.1.10 SFLASH_CSD_TRIM2_CSD Address = 0x0FFFF163 CSD Trim Data for (normal) CSD operation Address: 0x0FFFF163 Retention: Retained Bits SW Access HW Access Name TRIM8 [7:0] Bits Name Description 7 : 0 TRIM8 Trim data Default Value: X PSoC 4 Registers TRM, Document Number: 001-90002 Rev. *E...
  • Page 199 SFLASH_IMO_TRIM_USBMODE_24 7.1.11 SFLASH_IMO_TRIM_USBMODE_24 Address = 0x0FFFF1BE USB IMO TRIM 24MHz Address: 0x0FFFF1BE Retention: Retained Bits SW Access HW Access Name TRIM_24 [7:0] Bits Name Description 7 : 0 TRIM_24 TRIM value for IMO with USB at 24MHz Default Value: X PSoC 4 Registers TRM, Document Number: 001-90002 Rev.
  • Page 200 SFLASH_IMO_TRIM_USBMODE_48 7.1.12 SFLASH_IMO_TRIM_USBMODE_48 Address = 0x0FFFF1BF USB IMO TRIM 48MHz Address: 0x0FFFF1BF Retention: Retained Bits SW Access HW Access Name TRIM_24 [7:0] Bits Name Description 7 : 0 TRIM_24 TRIM value for IMO with USB at 24MHz Default Value: X PSoC 4 Registers TRM, Document Number: 001-90002 Rev.
  • Page 201 SFLASH_IMO_TCTRIM_LT0 7.1.13 SFLASH_IMO_TCTRIM_LT0 Address = 0x0FFFF1CC IMO TempCo Trim Register (SRSS-Lite) Address: 0x0FFFF1CC Retention: Retained Bits SW Access None HW Access None Name None TCTRIM [6:5] STEPSIZE [4:0] Bits Name Description 6 : 5 TCTRIM IMO temperature compesation trim. These bits are determined at manufacturing time to adjust for temperature dependence.
  • Page 202 SFLASH_IMO_TRIM_LT0 7.1.14 SFLASH_IMO_TRIM_LT0 Address = 0x0FFFF1E5 IMO Frequency Trim Register (SRSS-Lite) Address: 0x0FFFF1E5 Retention: Retained Bits SW Access HW Access Name OFFSET [7:0] Bits Name Description 7 : 0 OFFSET Frequency trim bits. These bits are determined at manufacturing time for each FREQ setting (IMO_TRIM2) and stored in SFLASH.

  • Page 203: Spcif Registers

    SPCIF Registers This section discusses the SPCIF registers of PSoC 4 device. It lists all the registers in mapping tables, in address order. SPCIF Register Mapping Details Register Address Description SPCIF_GEOMETRY 0x40110000 Flash/NVL geometry information SPCIF_INTR 0x401107F0 SPCIF interrupt request register SPCIF_INTR_SET 0x401107F4 SPCIF interrupt set request register...
  • Page 204 SPCIF_GEOMETRY 8.1.1 SPCIF_GEOMETRY Address = 0x40110000 Flash/NVL geometry information Address: 0x40110000 Retention: Retained Bits SW Access HW Access Name FLASH [7:0] Bits SW Access HW Access Name FLASH [15:8] Bits SW Access HW Access Name FLASH_ROW [23:22] NUM_FLASH [21:20] SFLASH [19:16] Bits SW Access None...
  • Page 205 SPCIF_GEOMETRY 8.1.1 SPCIF_GEOMETRY (continued) 21 : 20 NUM_FLASH Number of flash macros (chip dependent): "0": 1 flash macro "1": 2 flash macros "2": 3 flash macros "3": 4 flash macros Default Value: Undefined 19 : 16 SFLASH Supervisory flash capacity in 256 Byte multiples (chip dependent). If multiple flash macros are present, this field provides the supervisory flash capacity of all flash macros together: "0": 256 Bytes.
  • Page 206 SPCIF_INTR 8.1.2 SPCIF_INTR Address = 0x401107F0 SPCIF interrupt request register Address: 0x401107F0 Retention: Not Retained Bits SW Access None RW1C HW Access None RW1S Name None [7:1] TIMER Bits SW Access None HW Access None Name None [15:8] Bits SW Access None HW Access None...
  • Page 207 SPCIF_INTR_SET 8.1.3 SPCIF_INTR_SET Address = 0x401107F4 SPCIF interrupt set request register Address: 0x401107F4 Retention: Not Retained Bits SW Access None RW1S HW Access None Name None [7:1] TIMER Bits SW Access None HW Access None Name None [15:8] Bits SW Access None HW Access None...
  • Page 208 SPCIF_INTR_MASK 8.1.4 SPCIF_INTR_MASK Address = 0x401107F8 SPCIF interrupt mask register Address: 0x401107F8 Retention: Retained Bits SW Access None HW Access None Name None [7:1] TIMER Bits SW Access None HW Access None Name None [15:8] Bits SW Access None HW Access None Name None [23:16]...
  • Page 209 SPCIF_INTR_MASKED 8.1.5 SPCIF_INTR_MASKED Address = 0x401107FC SPCIF interrupt masked request register Address: 0x401107FC Retention: Not Retained Bits SW Access None HW Access None Name None [7:1] TIMER Bits SW Access None HW Access None Name None [15:8] Bits SW Access None HW Access None...

  • Page 210: Srsslt Registers

    SRSSLT Registers This section discusses the SRSSLT registers of PSoC 4 device. It lists all the registers in mapping tables, in address order. SRSSLT Register Mapping Details Register Address Description PWR_CONTROL 0x40030000 Power Mode Control PWR_KEY_DELAY 0x40030004 Power System Key&Delay Register PWR_DDFT_SELECT 0x4003000C Power DDFT Mode Selection Register...
  • Page 211 PWR_CONTROL 9.1.1 PWR_CONTROL Address = 0x40030000 Power Mode Control Address: 0x40030000 Retention: Retained Bits SW Access None HW Access None Name DEBUG_- None [7:6] POWER_MODE [3:0] M_READY SESSION Bits SW Access None HW Access None Name None [15:8] Bits SW Access None HW Access None...
  • Page 212 PWR_CONTROL 9.1.1 PWR_CONTROL (continued) LPM_READY Indicates whether the low power mode regulator is ready to enter DEEPSLEEP mode. 0: If DEEPSLEEP mode is requested, device will enter SLEEP mode. When low power regula- tors are ready, device will automatically enter the originally requested mode. 1: Normal operation.
  • Page 213 PWR_KEY_DELAY 9.1.2 PWR_KEY_DELAY Address = 0x40030004 Power System Key Register Address: 0x40030004 Retention: Retained Bits SW Access HW Access Name WAKEUP_HOLDOFF [7:0] Bits SW Access None HW Access None Name None [15:10] WAKEUP_HOLDOFF [9:8] Bits SW Access None HW Access None Name None [23:16]...
  • Page 214 PWR_DDFT_SELECT 9.1.3 PWR_DDFT_SELECT Address = 0x4003000C Power DDFT Mode Selection Register Address: 0x4003000C Retention: Retained Bits SW Access HW Access Name DDFT1_SEL [7:4] DDFT0_SEL [3:0] Bits SW Access None HW Access None Name None [15:8] Bits SW Access None HW Access None Name None [23:16]...
  • Page 215 PWR_DDFT_SELECT 9.1.3 PWR_DDFT_SELECT (continued) 0x4: ACT_POWER_GOOD : act_power_good 0x5: ACT_REF_VALID : act_ref_valid 0x6: ACT_REG_VALID : act_reg_valid 0x7: ACT_COMP_OUT : act_comp_out 0x8: ACT_TEMP_HIGH : act_temp_high 0x9: DPSLP_COMP_OUT : dpslp_comp_out 0xa: DPSLP_POWER_UP : dpslp_power_up 0xb: AWAKE_DELAYED : awake_delayed 0xc: LPM_READY : lpm_ready 0xd: SLEEPHOLDACK_N : sleepholdack_n 0xe: GND :...
  • Page 216 PWR_DDFT_SELECT 9.1.3 PWR_DDFT_SELECT (continued) 0x0: WAKEUP : wakeup 0x1: AWAKE : awake 0x2: ACT_POWER_EN : act_power_en 0x3: ACT_POWER_UP : act_power_up 0x4: ACT_POWER_GOOD : act_power_good 0x5: ACT_REF_EN : srss_adft_control_act_ref_en 0x6: ACT_COMP_EN : srss_adft_control_act_comp_en 0x7: DPSLP_REF_EN : srss_adft_control_dpslp_ref_en 0x8: DPSLP_REG_EN : srss_adft_control_dpslp_reg_en 0x9: DPSLP_COMP_EN : srss_adft_control_dpslp_comp_en 0xa: OVER_TEMP_EN :...
  • Page 217 PWR_DDFT_SELECT 9.1.3 PWR_DDFT_SELECT (continued) 0xc: ADFT_BUF_EN : adft_buf_en 0xd: ATPG_OBSERVE : ATPG observe point (no functional purpose) 0xe: GND : 1'b0 0xf: PWR : 1'b1 PSoC 4 Registers TRM, Document Number: 001-90002 Rev. *E...
  • Page 218 TST_MODE 9.1.4 TST_MODE Address = 0x40030014 Test Mode Control Register Address: 0x40030014 Retention: Retained Bits SW Access None None HW Access None None Name SWD_CON- None [7:3] None NECTED Bits SW Access None HW Access None Name None [15:8] Bits SW Access None HW Access...
  • Page 219 TST_MODE 9.1.4 TST_MODE (continued) SWD_CONNECTED 0: SWD not active 1: SWD activated (Line Reset & Connect sequence passed) (Note: this bit replaces TST_CTRL.SWD_CONNECTED and is present in all M0S8 products ex- cept TSG4) Default Value: 0 PSoC 4 Registers TRM, Document Number: 001-90002 Rev. *E...
  • Page 220 CLK_SELECT 9.1.5 CLK_SELECT Address = 0x40030028 Clock Select Register Address: 0x40030028 Retention: Retained Bits SW Access HW Access Name SYSCLK_DIV [7:6] PUMP_SEL [5:4] HFCLK_DIV [3:2] HFCLK_SEL [1:0] Bits SW Access None HW Access None Name None [15:8] Bits SW Access None HW Access None...
  • Page 221 CLK_SELECT 9.1.5 CLK_SELECT (continued) 5 : 4 PUMP_SEL Selects clock source for charge pump clock. This clock is not guaranteed to be glitch free when changing any of its sources or settings. Default Value: 0 0x0: GND : No clock, connect to gnd 0x1: IMO : Use main IMO output 0x2: HFCLK :...
  • Page 222 CLK_ILO_CONFIG 9.1.6 CLK_ILO_CONFIG Address = 0x4003002C ILO Configuration Address: 0x4003002C Retention: Retained Bits SW Access None HW Access None Name None [7:0] Bits SW Access None HW Access None Name None [15:8] Bits SW Access None HW Access None Name None [23:16] Bits SW Access...
  • Page 223 CLK_IMO_CONFIG 9.1.7 CLK_IMO_CONFIG Address = 0x40030030 IMO Configuration Address: 0x40030030 Retention: Retained Bits SW Access None HW Access None Name None [7:0] Bits SW Access None HW Access None Name None [15:8] Bits SW Access None HW Access None Name None [23:16] Bits SW Access...
  • Page 224 CLK_DFT_SELECT 9.1.8 CLK_DFT_SELECT Address = 0x40030034 Clock DFT Mode Selection Register Address: 0x40030034 Retention: Retained Bits SW Access None HW Access None Name DFT_EDGE None DFT_DIV0 [5:4] DFT_SEL0 [3:0] Bits SW Access None HW Access None Name DFT_EDGE None DFT_DIV1 [13:12] DFT_SEL1 [11:8] Bits SW Access...
  • Page 225 CLK_DFT_SELECT 9.1.8 CLK_DFT_SELECT (continued) 0x1: DIV_BY_2 : Divide by 2 0x2: DIV_BY_4 : Divide by 4 0x3: DIV_BY_8 : Divide by 8 11 : 8 DFT_SEL1 Select signal for DFT output #1 Default Value: 0 0x0: NC : Disabled - output is 0 0x1: ILO : clk_ilo: ILO output 0x2: IMO :...
  • Page 226 CLK_DFT_SELECT 9.1.8 CLK_DFT_SELECT (continued) 0x9: SLPCTRLCLK : clk_slpctrl: clock provided to SleepController DFT_EDGE0 Edge sensitivity for in-line divider on output #0 (only relevant when DIV0>0). Default Value: 0 0x0: POSEDGE : Use posedge for divider 0x1: NEGEDGE : Use negedge for divider 5 : 4 DFT_DIV0 DFT Output Divide Down.
  • Page 227 CLK_DFT_SELECT 9.1.8 CLK_DFT_SELECT (continued) 0x4: EXTCLK : clk_ext: external clock input 0x5: HFCLK : clk_hf: root of the high-speed clock tree 0x6: LFCLK : clk_lf: root of the low-speed clock tree 0x7: SYSCLK : clk_sys: root of the CPU/AHB clock tree (gated version of clk_hf) 0x8: PUMPCLK : clk_pump: clock provided to charge pumps in FLASH and PA 0x9: SLPCTRLCLK :...
  • Page 228 WDT_DISABLE_KEY 9.1.9 WDT_DISABLE_KEY Address = 0x40030038 Watchdog Disable Key Register Address: 0x40030038 Retention: Retained Bits SW Access HW Access Name KEY [7:0] Bits SW Access HW Access Name KEY [15:8] Bits SW Access HW Access Name KEY [23:16] Bits SW Access HW Access Name KEY [31:24]...
  • Page 229 WDT_COUNTER 9.1.10 WDT_COUNTER Address = 0x4003003C Watchdog Counter Register Address: 0x4003003C Retention: Retained Bits SW Access HW Access Name COUNTER [7:0] Bits SW Access HW Access Name COUNTER [15:8] Bits SW Access None HW Access None Name None [23:16] Bits SW Access None HW Access...
  • Page 230 WDT_MATCH 9.1.11 WDT_MATCH Address = 0x40030040 Watchdog Match Register Address: 0x40030040 Retention: Retained Bits SW Access HW Access Name MATCH [7:0] Bits SW Access HW Access Name MATCH [15:8] Bits SW Access None HW Access None Name None [23:20] IGNORE_BITS [19:16] Bits SW Access None...
  • Page 231 SRSS_INTR 9.1.12 SRSS_INTR Address = 0x40030044 SRSS Interrupt Register Address: 0x40030044 Retention: Retained Bits SW Access None RW1C RW1C HW Access None Name TEMP_HIG WDT_- None [7:2] MATCH Bits SW Access None HW Access None Name None [15:8] Bits SW Access None HW Access None...
  • Page 232 SRSS_INTR_SET 9.1.13 SRSS_INTR_SET Address = 0x40030048 SRSS Interrupt Set Register Address: 0x40030048 Retention: Retained Bits SW Access None RW1S None HW Access None None Name TEMP_HIG None [7:2] None Bits SW Access None HW Access None Name None [15:8] Bits SW Access None HW Access...
  • Page 233 SRSS_INTR_MASK 9.1.14 SRSS_INTR_MASK Address = 0x4003004C SRSS Interrupt Mask Register Address: 0x4003004C Retention: Retained Bits SW Access None HW Access None Name TEMP_HIG WDT_- None [7:2] MATCH Bits SW Access None HW Access None Name None [15:8] Bits SW Access None HW Access None...
  • Page 234 RES_CAUSE 9.1.15 RES_CAUSE Address = 0x40030054 Reset Cause Observation Register Address: 0x40030054 Retention: Retained Bits SW Access None RW1C RW1C None RW1C HW Access None None Name RESET_- None [7:5] SET_PROT None [2:1] SOFT SET_WDT _FAULT Bits SW Access None HW Access None Name...
  • Page 235 PWR_BG_TRIM1 9.1.16 PWR_BG_TRIM1 Address = 0x40030F00 Bandgap Trim Register Address: 0x40030F00 Retention: Retained Bits SW Access None HW Access None Name None [7:6] REF_VTRIM [5:0] Bits SW Access None HW Access None Name None [15:8] Bits SW Access None HW Access None Name None [23:16]...
  • Page 236 PWR_BG_TRIM2 9.1.17 PWR_BG_TRIM2 Address = 0x40030F04 Bandgap Trim Register Address: 0x40030F04 Retention: Retained Bits SW Access None HW Access None Name None [7:6] REF_ITRIM [5:0] Bits SW Access None HW Access None Name None [15:8] Bits SW Access None HW Access None Name None [23:16]...
  • Page 237 CLK_IMO_SELECT 9.1.18 CLK_IMO_SELECT Address = 0x40030F08 IMO Frequency Select Register Address: 0x40030F08 Retention: Retained Bits SW Access None HW Access None Name None [7:3] FREQ [2:0] Bits SW Access None HW Access None Name None [15:8] Bits SW Access None HW Access None Name...
  • Page 238 CLK_IMO_SELECT 9.1.18 CLK_IMO_SELECT (continued) 0x4: 40_MHZ : IMO runs at 40 MHz 0x5: 44_MHZ : IMO runs at 44 MHz 0x6: 48_MHZ : IMO runs at 48 MHz PSoC 4 Registers TRM, Document Number: 001-90002 Rev. *E...
  • Page 239 CLK_IMO_TRIM1 9.1.19 CLK_IMO_TRIM1 Address = 0x40030F0C IMO Trim Register Address: 0x40030F0C Retention: Retained Bits SW Access HW Access Name OFFSET [7:0] Bits SW Access None HW Access None Name None [15:8] Bits SW Access None HW Access None Name None [23:16] Bits SW Access None...
  • Page 240 CLK_IMO_TRIM2 9.1.20 CLK_IMO_TRIM2 Address = 0x40030F10 IMO Trim Register Address: 0x40030F10 Retention: Retained Bits SW Access None HW Access None Name None [7:3] FSOFFSET [2:0] Bits SW Access None HW Access None Name None [15:8] Bits SW Access None HW Access None Name None [23:16]...
  • Page 241 PWR_PWRSYS_TRIM1 9.1.21 PWR_PWRSYS_TRIM1 Address = 0x40030F14 Power System Trim Register Address: 0x40030F14 Retention: Retained Bits SW Access HW Access Name SPARE_TRIM [7:4] DPSLP_REF_TRIM [3:0] Bits SW Access None HW Access None Name None [15:8] Bits SW Access None HW Access None Name None [23:16]...
  • Page 242 CLK_IMO_TRIM3 9.1.22 CLK_IMO_TRIM3 Address = 0x40030F18 IMO Trim Register Address: 0x40030F18 Retention: Retained Bits SW Access None HW Access None Name None TCTRIM [6:5] STEPSIZE [4:0] Bits SW Access None HW Access None Name None [15:8] Bits SW Access None HW Access None Name...

  • Page 243: Tcpwm Registers

    TCPWM Registers This section discusses the TCPWM registers of PSoC 4 device. It lists all the registers in mapping tables, in address order. 10.1 TCPWM Register Mapping Details Register Address Description TCPWM_CTRL 0x40050000 TCPWM control register 0. TCPWM_CMD 0x40050008 TCPWM command register. TCPWM_INTR_CAUSE 0x4005000C TCPWM Counter interrupt cause register.
  • Page 244 TCPWM_CTRL 10.1.1 TCPWM_CTRL Address = 0x40050000 TCPWM control register 0. Address: 0x40050000 Retention: Not Retained Bits SW Access None HW Access None Name COUNTER_ None [7:1] ENABLED Bits SW Access None HW Access None Name None [15:8] Bits SW Access None HW Access None...
  • Page 245 TCPWM_CMD 10.1.2 TCPWM_CMD Address = 0x40050008 TCPWM command register. Address: 0x40050008 Retention: Not Retained Bits SW Access None RW1S HW Access None RW1C Name COUNTER_ None [7:1] CAPTURE Bits SW Access None RW1S HW Access None RW1C Name COUNTER_ None [15:9] RELOAD Bits SW Access...
  • Page 246 TCPWM_INTR_CAUSE 10.1.3 TCPWM_INTR_CAUSE Address = 0x4005000C TCPWM Counter interrupt cause register. Address: 0x4005000C Retention: Not Retained Bits SW Access None HW Access None Name COUNTER_ None [7:1] Bits SW Access None HW Access None Name None [15:8] Bits SW Access None HW Access None...
  • Page 247 TCPWM_CNT0_CTRL 10.1.4 TCPWM_CNT0_CTRL Address = 0x40050100 Counter control register Address: 0x40050100 Retention: Retained Bits SW Access None HW Access None Name AUTO_RE- PWM_SYN- AUTO_RE- None [7:4] M_STOP_O LOAD_PE- C_KILL LOAD_CC N_KILL RIOD Bits SW Access HW Access Name GENERIC [15:8] Bits SW Access None...
  • Page 248 TCPWM_CNT0_CTRL 10.1.4 TCPWM_CNT0_CTRL (continued) 0x4: PWM : Pulse width modulation (PWM) mode 0x5: PWM_DT : PWM with deadtime insertion mode 0x6: PWM_PR : Pseudo random pulse width modulation 21 : 20 QUADRATURE_MODE In QUAD mode selects quadrature encoding mode (X1/X2/X4). In PWM, PWM_DT and PWM_PR modes, these two bits can be used to invert "dt_line_out"...
  • Page 249 TCPWM_CNT0_CTRL 10.1.4 TCPWM_CNT0_CTRL (continued) 0x1: COUNT_DOWN : Count down (to "0"). An underflow event is generated when the counter reaches "0". A terminal count event is generated when the counter reaches "0". 0x2: COUNT_UPDN1 : Count up (to PERIOD), then count down (to "0"). An overflow event is generated when the count- er reaches PERIOD.
  • Page 250 TCPWM_CNT0_CTRL 10.1.4 TCPWM_CNT0_CTRL (continued) 0x7: DIVBY128 : Divide by 128 (other-than-PWM_DT mode) PWM_STOP_ON_KILL Specifies whether the counter stops on a kill events: '0': kill event does NOT stop counter. '1': kill event stops counter. This field has a function in PWM, PWM_DT and PWM_PR modes only. Default Value: 0 PWM_SYNC_KILL Specifies asynchronous/synchronous kill behavior:...
  • Page 251 TCPWM_CNT0_STATUS 10.1.5 TCPWM_CNT0_STATUS Address = 0x40050104 Counter status register Address: 0x40050104 Retention: Not Retained Bits SW Access None HW Access None Name None [7:1] DOWN Bits SW Access HW Access Name GENERIC [15:8] Bits SW Access None HW Access None Name None [23:16] Bits...
  • Page 252 TCPWM_CNT0_COUNTER 10.1.6 TCPWM_CNT0_COUNTER Address = 0x40050108 Counter count register Address: 0x40050108 Retention: Retained Bits SW Access HW Access Name COUNTER [7:0] Bits SW Access HW Access Name COUNTER [15:8] Bits SW Access None HW Access None Name None [23:16] Bits SW Access None HW Access...
  • Page 253 TCPWM_CNT0_CC 10.1.7 TCPWM_CNT0_CC Address = 0x4005010C Counter compare/capture register Address: 0x4005010C Retention: Retained Bits SW Access HW Access Name CC [7:0] Bits SW Access HW Access Name CC [15:8] Bits SW Access None HW Access None Name None [23:16] Bits SW Access None HW Access...
  • Page 254 TCPWM_CNT0_CC_BUFF 10.1.8 TCPWM_CNT0_CC_BUFF Address = 0x40050110 Counter buffered compare/capture register Address: 0x40050110 Retention: Retained Bits SW Access HW Access Name CC [7:0] Bits SW Access HW Access Name CC [15:8] Bits SW Access None HW Access None Name None [23:16] Bits SW Access None...
  • Page 255 TCPWM_CNT0_PERIOD 10.1.9 TCPWM_CNT0_PERIOD Address = 0x40050114 Counter period register Address: 0x40050114 Retention: Retained Bits SW Access HW Access Name PERIOD [7:0] Bits SW Access HW Access Name PERIOD [15:8] Bits SW Access None HW Access None Name None [23:16] Bits SW Access None HW Access...
  • Page 256 TCPWM_CNT0_PERIOD_BUFF 10.1.10 TCPWM_CNT0_PERIOD_BUFF Address = 0x40050118 Counter buffered period register Address: 0x40050118 Retention: Retained Bits SW Access HW Access Name PERIOD [7:0] Bits SW Access HW Access Name PERIOD [15:8] Bits SW Access None HW Access None Name None [23:16] Bits SW Access None...
  • Page 257 TCPWM_CNT0_TR_CTRL0 10.1.11 TCPWM_CNT0_TR_CTRL0 Address = 0x40050120 Counter trigger control register 0 Address: 0x40050120 Retention: Retained Bits SW Access HW Access Name COUNT_SEL [7:4] CAPTURE_SEL [3:0] Bits SW Access HW Access Name STOP_SEL [15:12] RELOAD_SEL [11:8] Bits SW Access None HW Access None Name None [23:20]...
  • Page 258 TCPWM_CNT0_TR_CTRL0 10.1.11 TCPWM_CNT0_TR_CTRL0 (continued) 3 : 0 CAPTURE_SEL Selects one of the 16 input triggers as a capture trigger. Input trigger 0 is always '0' and input trigger is always '1'. In the PWM, PWM_DT and PWM_PR modes this trigger is used to switch the values if the compare and period registers with their buffer counterparts.
  • Page 259 TCPWM_CNT0_TR_CTRL1 10.1.12 TCPWM_CNT0_TR_CTRL1 Address = 0x40050124 Counter trigger control register 1 Address: 0x40050124 Retention: Retained Bits SW Access HW Access Name STOP_EDGE [7:6] RELOAD_EDGE [5:4] COUNT_EDGE [3:2] CAPTURE_EDGE [1:0] Bits SW Access None HW Access None Name None [15:10] START_EDGE [9:8] Bits SW Access None...
  • Page 260 TCPWM_CNT0_TR_CTRL1 10.1.12 TCPWM_CNT0_TR_CTRL1 (continued) 0x3: NO_EDGE_DET : No edge detection, use trigger as is. 7 : 6 STOP_EDGE A stop event, will stop the counter; i.e. it will no longer be running. Stopping will NOT disable the counter. Default Value: 3 0x0: RISING_EDGE : Rising edge.
  • Page 261 TCPWM_CNT0_TR_CTRL1 10.1.12 TCPWM_CNT0_TR_CTRL1 (continued) 0x1: FALLING_EDGE : Falling edge. Any falling edge generates an event. 0x2: BOTH_EDGES : Rising AND falling edge. Any odd amount of edges generates an event. 0x3: NO_EDGE_DET : No edge detection, use trigger as is. 1 : 0 CAPTURE_EDGE A capture event will copy the counter value into the CC register.
  • Page 262 TCPWM_CNT0_TR_CTRL2 10.1.13 TCPWM_CNT0_TR_CTRL2 Address = 0x40050128 Counter trigger control register 2 Address: 0x40050128 Retention: Retained Bits SW Access None HW Access None Name UNDERFLOW_MODE None [7:6] OVERFLOW_MODE [3:2] CC_MATCH_MODE [1:0] [5:4] Bits SW Access None HW Access None Name None [15:8] Bits SW Access None...
  • Page 263 TCPWM_CNT0_TR_CTRL2 10.1.13 TCPWM_CNT0_TR_CTRL2 (continued) 0x3: NO_CHANGE : No Change 3 : 2 OVERFLOW_MODE Determines the effect of a counter overflow event (COUNTER reaches PERIOD) on the "line_out" output signals. Default Value: 3 0x0: SET : Set to '1' 0x1: CLEAR : Set to '0' 0x2: INVERT : Invert...
  • Page 264 TCPWM_CNT0_INTR 10.1.14 TCPWM_CNT0_INTR Address = 0x40050130 Interrupt request register. Address: 0x40050130 Retention: Not Retained Bits SW Access None RW1C RW1C HW Access None RW1S RW1S Name None [7:2] CC_MATCH Bits SW Access None HW Access None Name None [15:8] Bits SW Access None HW Access...
  • Page 265 TCPWM_CNT0_INTR_SET 10.1.15 TCPWM_CNT0_INTR_SET Address = 0x40050134 Interrupt set request register. Address: 0x40050134 Retention: Not Retained Bits SW Access None RW1S RW1S HW Access None Name None [7:2] CC_MATCH Bits SW Access None HW Access None Name None [15:8] Bits SW Access None HW Access None...
  • Page 266 TCPWM_CNT0_INTR_MASK 10.1.16 TCPWM_CNT0_INTR_MASK Address = 0x40050138 Interrupt mask register. Address: 0x40050138 Retention: Retained Bits SW Access None HW Access None Name None [7:2] CC_MATCH Bits SW Access None HW Access None Name None [15:8] Bits SW Access None HW Access None Name None [23:16]...
  • Page 267 TCPWM_CNT0_INTR_MASKED 10.1.17 TCPWM_CNT0_INTR_MASKED Address = 0x4005013C Interrupt masked request register Address: 0x4005013C Retention: Not Retained Bits SW Access None HW Access None Name None [7:2] CC_MATCH Bits SW Access None HW Access None Name None [15:8] Bits SW Access None HW Access None Name...

  • Page 268: Rom Table Registers

    ROM Table Registers This section discusses the ROM Table registers. It lists all the registers in mapping tables, in address order. 11.1 Register Details Register Address Description ROMTABLE_ADDR 0xF0000000 Link to Cortex M0 ROM Table. ROMTABLE_DID 0xF0000FCC Device Type Identifier register. ROMTABLE_PID4 0xF0000FD0 Peripheral Identification Register 4.
  • Page 269 ROMTABLE_ADDR 11.1.1 ROMTABLE_ADDR Address = 0xF0000000 Link to Cortex M0 ROM Table. Address: 0xF0000000 Retention: Retained Bits SW Access None HW Access None Name FOR- None [7:2] PRESENT MAT_32BIT Bits SW Access None HW Access None Name ADDR_OFFSET [15:12] None [11:8] Bits SW Access HW Access...
  • Page 270 ROMTABLE_DID 11.1.2 ROMTABLE_DID Address = 0xF0000FCC Device Type Identifier register. Address: 0xF0000FCC Retention: Retained Bits SW Access HW Access Name VALUE [7:0] Bits SW Access HW Access Name VALUE [15:8] Bits SW Access HW Access Name VALUE [23:16] Bits SW Access HW Access Name VALUE [31:24]...
  • Page 271 ROMTABLE_PID4 11.1.3 ROMTABLE_PID4 Address = 0xF0000FD0 Peripheral Identification Register 4. Address: 0xF0000FD0 Retention: Retained Bits SW Access HW Access Name COUNT [7:4] JEP_CONTINUATION [3:0] Bits SW Access None HW Access None Name None [15:8] Bits SW Access None HW Access None Name None [23:16]...
  • Page 272 ROMTABLE_PID5 11.1.4 ROMTABLE_PID5 Address = 0xF0000FD4 Peripheral Identification Register 5. Address: 0xF0000FD4 Retention: Retained Bits SW Access HW Access Name VALUE [7:0] Bits SW Access HW Access Name VALUE [15:8] Bits SW Access HW Access Name VALUE [23:16] Bits SW Access HW Access Name VALUE [31:24]...
  • Page 273 ROMTABLE_PID6 11.1.5 ROMTABLE_PID6 Address = 0xF0000FD8 Peripheral Identification Register 6. Address: 0xF0000FD8 Retention: Retained Bits SW Access HW Access Name VALUE [7:0] Bits SW Access HW Access Name VALUE [15:8] Bits SW Access HW Access Name VALUE [23:16] Bits SW Access HW Access Name VALUE [31:24]...
  • Page 274 ROMTABLE_PID7 11.1.6 ROMTABLE_PID7 Address = 0xF0000FDC Peripheral Identification Register 7. Address: 0xF0000FDC Retention: Retained Bits SW Access HW Access Name VALUE [7:0] Bits SW Access HW Access Name VALUE [15:8] Bits SW Access HW Access Name VALUE [23:16] Bits SW Access HW Access Name VALUE [31:24]...
  • Page 275 ROMTABLE_PID0 11.1.7 ROMTABLE_PID0 Address = 0xF0000FE0 Peripheral Identification Register 0. Address: 0xF0000FE0 Retention: Retained Bits SW Access HW Access Name PN_MIN [7:0] Bits SW Access None HW Access None Name None [15:8] Bits SW Access None HW Access None Name None [23:16] Bits SW Access...
  • Page 276 ROMTABLE_PID1 11.1.8 ROMTABLE_PID1 Address = 0xF0000FE4 Peripheral Identification Register 1. Address: 0xF0000FE4 Retention: Retained Bits SW Access HW Access Name JEPID_MIN [7:4] PN_MAJ [3:0] Bits SW Access None HW Access None Name None [15:8] Bits SW Access None HW Access None Name None [23:16]...
  • Page 277 ROMTABLE_PID2 11.1.9 ROMTABLE_PID2 Address = 0xF0000FE8 Peripheral Identification Register 2. Address: 0xF0000FE8 Retention: Retained Bits SW Access None HW Access None Name REV [7:4] None JEPID_MAJ [2:0] Bits SW Access None HW Access None Name None [15:8] Bits SW Access None HW Access None...
  • Page 278 ROMTABLE_PID3 11.1.10 ROMTABLE_PID3 Address = 0xF0000FEC Peripheral Identification Register 3. Address: 0xF0000FEC Retention: Retained Bits SW Access HW Access Name REV_AND [7:4] CM [3:0] Bits SW Access None HW Access None Name None [15:8] Bits SW Access None HW Access None Name None [23:16]...
  • Page 279 ROMTABLE_CID0 11.1.11 ROMTABLE_CID0 Address = 0xF0000FF0 Component Identification Register 0. Address: 0xF0000FF0 Retention: Retained Bits SW Access HW Access Name VALUE [7:0] Bits SW Access HW Access Name VALUE [15:8] Bits SW Access HW Access Name VALUE [23:16] Bits SW Access HW Access Name VALUE [31:24]...
  • Page 280 ROMTABLE_CID1 11.1.12 ROMTABLE_CID1 Address = 0xF0000FF4 Component Identification Register 1. Address: 0xF0000FF4 Retention: Retained Bits SW Access HW Access Name VALUE [7:0] Bits SW Access HW Access Name VALUE [15:8] Bits SW Access HW Access Name VALUE [23:16] Bits SW Access HW Access Name VALUE [31:24]...
  • Page 281 ROMTABLE_CID2 11.1.13 ROMTABLE_CID2 Address = 0xF0000FF8 Component Identification Register 2. Address: 0xF0000FF8 Retention: Retained Bits SW Access HW Access Name VALUE [7:0] Bits SW Access HW Access Name VALUE [15:8] Bits SW Access HW Access Name VALUE [23:16] Bits SW Access HW Access Name VALUE [31:24]...
  • Page 282 ROMTABLE_CID3 11.1.14 ROMTABLE_CID3 Address = 0xF0000FFC Component Identification Register 3. Address: 0xF0000FFC Retention: Retained Bits SW Access HW Access Name VALUE [7:0] Bits SW Access HW Access Name VALUE [15:8] Bits SW Access HW Access Name VALUE [23:16] Bits SW Access HW Access Name VALUE [31:24]...

  • Page 283: Revision History

    Revision History Revision History Document Title: PSoC 4000 Family PSoC(R) 4 Registers Technical Reference Manual (TRM) Document Number: 001-90002 Origin of Revision ECN# Issue Date Description of Change Change 4186400 11/11/13 NIDH Specification for new silicon. Updated the clock divider descriptions in Clock trim and peripheral divider registers. Updated the IO select 4316501 04/10/14 NIDH...

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