Overview; Requirements - Xilinx Virtex-7 FPGA VC7215 Getting Started Manual

VC7215 IBERT Getting Started Guide

Overview

This document provides a procedure for setting up the Virtex®-7 FPGA VC7215 GTH
Transceiver Characterization Board to run the Integrated Bit Error Ratio Test (IBERT)
demonstration using the Vivado® Design Suite. The designs required to run the IBERT
demonstrations are stored in three Secure Digital (SD) memory cards that are provided
with the VC7215 board. The demonstration shows the capabilities of the Virtex-7
XC7VX690T FPGA GTH transceiver.
The VC7215 board is described in detail in VC7215 Virtex-7 FPGA GTH Transceiver
Characterization Board User Guide (UG972)
The IBERT demonstrations operate one GTH Quad at a time. The procedure consists of:
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Requirements

The hardware and software required to run the GTH IBERT demonstrations are:
•
VC7215 Getting Started Guide
UG970 (v7.0) November 24, 2014
Setting Up the VC7215 Board, page 6
Extracting the Project Files, page 7
Connecting the GTH Transceivers and Reference Clocks, page 8
Configuring the FPGA, page 13
Setting Up Vivado Design Suite, page 15
Starting the SuperClock-2 Module, page 18
Viewing GTH Transceiver Operation, page 24
Closing the IBERT Demonstration, page 25
VC7215 Virtex-7 FPGA GTH Transceiver Characterization Board. Includes:
• Three SD cards labeled IBERT #1, IBERT #2, and IBERT#3 containing the IBERT
demonstration designs
• One Samtec BullsEye cable
• Eight SMA female-to-female (F-F) adapters
• Six 50Ω SMA terminators
• Two GTH transceiver power supply modules (installed on board)
• SuperClock-2 module, Rev 1.0 (installed on board)
• 12V DC power adapter
• USB cable, standard-A plug to Micro-B plug
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