Xilinx Virtex-7 FPGA VC7215 Getting Started Manual page 21

4.
X-Ref Target - Figure 1-16
VC7215 Getting Started Guide
UG970 (v7.0) November 24, 2014
To view the SuperClock-2 settings in the VIO core, select the probe signal from the
Debug Probes window and drag it to the VIO-hw_vio_1 window. For example, the
frequencies, ROM addresses, and start signals are selected
Note:
The ROM address values for the Si5368 and Si570 devices (that is, si5368_addr[6:0]
and si570_addr[6:0]) are preset to 3 to produce an output frequency of 325.00 MHz. Entering a
different ROM address changes the reference clock(s) frequency. The complete list of
pre-programmed SuperClock-2 frequencies and their associated ROM addresses is provided in
Table 1-2, page 25.
Figure 1-16: SuperClock-2 Module VIO Core
www.xilinx.com
Running the GTH IBERT Demonstration
(Figure 1-16).
Send Feedback
21