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Xilinx Virtex-7 FPGA VC7215 Getting Started Manual page 37

Characterization kit ibert
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13. In the Sources window, Design Sources should now reflect that the SuperClock-2
X-Ref Target - Figure 1-30
VC7215 Getting Started Guide
UG970 (v7.0) November 24, 2014
module is part of the example IBERT design
Figure 1-30: Design Sources File Hierarchy
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Creating the GTH IBERT Core
(Figure
1-30).
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