Revision History; Chapter 1: Vc7215 Ibert Getting Started Guide - Xilinx Virtex-7 FPGA VC7215 Getting Started Manual

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Revision History

The following table shows the revision history for this document.
Date Version
07/10/2013 1.0
10/31/2013 2.0
12/18/2013 3.0
04/16/2014 4.0
06/12/2014 5.0
10/08/2014 6.0
11/24/2014 7.0
VC7215 Getting Started Guide
Initial Xilinx release.
Updated for Vivado® Design Suite 2013.3.
Updated most figures in Chapter 1, VC7215 IBERT Getting Started
was renamed Design Sources File Hierarchy. Figure 1-31, Synthesize Out-Of-Context Module
was deleted. The name of the project files ZIP file changed to
rdf0294-vc7215-ibert-2013-3.zip. Updated
Resources links.
Updated for Vivado Design Suite 2013.4. Updated
Updated Figure 1-19, Figure
Updated for Vivado Design Suite 2014.1. Updated most graphics in Chapter 1 from
Figure 1-10 on. File lists changed under
name changed to rdf0294-vc7215-ibert-2014-1.zip. The section Launching
Vivado Design Suite was changed to
of RX Bit Errors was added.
Updated for Vivado Design Suite 2014.2. Updated
Figure 1-20, Figure 1-23, Figure
Figure 1-35. Updated Viewing GTH Transceiver
Updated for Vivado Design Suite 2014.3. Updated
Figure 1-21, Figure 1-23, Figure
information to Starting the SuperClock-2
C_USER_SCAN_CHAIN* was changed to 3 in
Updated for Vivado Design Suite 2014.4. The name of the project files ZIP file changed
to rdf0294-vc7215-ibert-2014-4.zip. Updated
Figure 1-23.
www.xilinx.com
Revision
Appendix A, Additional
Figure 1-10
1-20, Figure 1-23, Figure 1-27, and
Extracting the Project
Setting Up Vivado Design
Figure
1-27, Figure 1-30, Figure
Operation.
Figure
1-27, and Figure 1-33. Added device programming
Module. Updated
Figure
Guide. Figure 1-30
through Figure 1-15.
Figure 1-28.
Files. The ZIP project file
Suite. The section In Case
1-10, Figure 1-11, Figure
1-32, Figure 1-33, and
1-10, Figure 1-11, Figure
In Case of RX Bit Errors.
1-33.
Figure 1-10, Figure 1-19, and
UG970 (v7.0) November 24, 2014
1-19,
1-19,