Xilinx Virtex-7 FPGA VC7215 Getting Started Manual page 35

11. In the new window, select Tools > Run Tcl Script. In the Run Script window,
X-Ref Target - Figure 1-28
VC7215 Getting Started Guide
UG970 (v7.0) November 24, 2014
navigate to add_scm2.tcl in the extracted files and press OK. The SuperClock-2
Module Design Sources and Constraints are automatically added to the example
design (Figure 1-28).
Figure 1-28: Sources after Running add_scm2.tcl
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Creating the GTH IBERT Core
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