ARM MPS3 Technical Reference Manual page 8

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SMALL CAPITALS
Timing diagrams
The following figure explains the components used in timing diagrams. Variations, when they occur,
have clear labels. You must not assume any timing information that is not explicit in the diagrams.
Shaded bus and signal areas are undefined, so the bus or signal can assume any value within the shaded
area at that time. The actual level is unimportant and does not affect normal operation.
Signals
The signal conventions are:
Signal level
Lowercase n
Additional reading
This book contains information that is specific to this product. See the following documents for other
relevant information.
Arm publications
100765_0000_04_en
Encloses replaceable terms for assembler syntax where they appear in code or code fragments.
For example:
MRC p15, 0, <Rd>, <CRn>, <CRm>, <Opcode_2>
Used in body text for a few terms that have specific technical meanings, that are defined in the
Arm Glossary. For example,
®
.
UNPREDICTABLE
The level of an asserted signal depends on whether the signal is active-HIGH or active-LOW.
Asserted means:
• HIGH for active-HIGH signals.
• LOW for active-LOW signals.
At the start or end of a signal name, n denotes an active-LOW signal.
• Arm Cortex -M System Design Kit Technical Reference Manual (DDI 0479).
® ®
• Application Note AN524 Example SSE
• Application Note AN533 Blinky example FPGA image for the MPS3 Prototyping Board
(DAI 0533)
• Arm CoreLink SIE ‑ 200 System IP for Embedded Technical Reference Manual (DDI 0571).
® ™
• Arm CoreLink SSE-200 Subsystem Technical Overview (DTO 0051).
® ™
• Arm CoreLink SSE-100 Subsystem Technical Reference Manual (DDI 0551).
® ™
• Arm DS-5 Arm DSTREAM User Guide (100955).
®
• Arm DS-5 Using the Debug Hardware Configuration Utilities (DUI 0498).
®
• CoreSight Components Technical Reference Manual (DDI 0314).
™
• CoreSight Trace Memory Controller Technical Reference Manual (DDI 0461).
™
Copyright © 2017–2020 Arm Limited or its affiliates. All rights
,
IMPLEMENTATION DEFINED IMPLEMENTATION SPECIFIC
Figure 1 Key to timing diagram conventions
‑ 200 Subsystem for MPS3 (DAI 0524).
reserved.
Non-Confidential
Preface
About this book
, , and
UNKNOWN
Clock
HIGH to LOW
Transient
HIGH/LOW to HIGH
Bus stable
Bus to high impedance
Bus change
High impedance to stable bus
8