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2.9
Video HDLCD interface
The HDMI controller and HDMI connector on the MPS3 board enable you to implement an HDLCD
interface.
The external controller is a frame buffer device that can display up to 1920 × 1080p resolution at 60fps.
Support for higher resolutions up to 1080p depends on the timing performance of your FPGA image.
The HDMI controller also supports I
The following figure shows a video HDLCD interface example design.
MPS3 FPGA Prototyping Board
Related information
A.7 HDMI Type A female connector on page Appx-A-85
1.3 Location of components on the MPS3 board on page 1-15
100765_0000_04_en
Note
2
S audio from the FPGA.
Processor
Bus matrix
Dynamic
2
2
I
S
I
C
Memory
Controller
DDR4
Figure 2-14 MPS3 board video HDLCD interface example design
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Non-Confidential
FPGA
HDLCD
24-bit RGB data,
synch and clock
HDMI
controller
TDA 19988
HDMI
reserved.
2 Hardware description
2.9 Video HDLCD interface
PLL
23.75MHz
OSC5
2-36
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