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•
An
images.txt
configuration:
•
An application note
— The number of FPGAs on the board.
— The number of oscillators and their frequencies.
— FPGA image file.
— Details of the SCC registers.
The following example shows a typical MPS3 board configuration
BOARD: HBI0309B
TITLE: Motherboard configuration file
[MCCS]
MBBIOS mbb_v132.ebf
[APPLICATION NOTE]
APPFILE: AN524\an524_v1.txt
The following example shows a typical MPS3 board configuration application note
BOARD: HBI0309
TITLE: AN524 application note configuration file
[FPGAS]
TOTALFPGAS: 1
F0FILE: an524_v1.bit
F0MODE: FPGA
[OSCCLKS]
TOTALOSCCLKS: 7
;Clock generators OSC1 to OSC5 connect to FPGA top level signals
;OSCCLK[1] to OSCCLK[5] respectively.
;Clockgen OSC0 Drives XTAL1/CLKIN of LAN9220 Ethernet controller.
;FPGA top level signal OSCCLK[0] is driven by a fixed 24MHz reference.
;Clockgen OSC0 does not connect to FPGA top level signal OSCCLK[0].
;Clockgen OSC6 drives the DDR reference clock c0_sys_clk_p/n.
OSC0: 25.0
;
24.0
OSC1: 32.0
OSC2: 50.0
OSC3: 50.0
OSC4: 24.576
OSC5: 23.75.0
OSC6: 100.0
[HARDWARE CONTROL]
ASSERTNPOR: TRUE
LEGACYRST: FALSE
CPUWAIT: 0x00000002
[PERIPHERAL SUPPORT]
FPGA_SMB: TRUE
FPGA_SCC: TRUE
SCCREG: 0x05300000
FPGA_DDR: TRUE
DDRBASE: 0x05208000
FPGA_SYSREG: TRUE
FPGAREG: 0x05302000
FPGA_REMAP: TRUE
REMAPREG: 0x05300000
REMAP: BRAM
REMAPVAL: 0
FPGA_HDMI: FALSE
HDMIBASE: 0x05207000
FPGA_LAN: TRUE
LANBASE: 0x05400000
FPGA_RTC: TRUE
RTCBASE: 0x0530B000
FPGA_QSPI: TRUE
100765_0000_04_en
file that defines the
.axf
file that defines:
.txt
;MB BIOS IMAGE
;Please select the required processor
;AN524 Cortex M33 SSE200 Subsystem for MPS3
;Total Number of FPGAS
;FPGA0 Filename
;FPGA0 Programming Mode
; Ethernet reference 25MHz
; OSCCLK[1]
; OSCCLK[2]
; OSCCLK[3]
; OSCCLK[4]
; OSCCLK[5]
; GTX clock (DDR)
;External resets assert nPOR
;Legacy CB_nPOR/CB_nRST reset mode
;CPUWAIT value, set to 0xFFFFFFFF when using CB_nRST
;SMB interface is supported (MCC_SMC<>FPGA_SMB)
;SCC interface is supported
;SCC registers base address
;DDR interface is supported
;DDR I2C register address
;System register interface is supported
;System registers base address
;REMAP interface is supported
;REMAP register address
;REMAP boot device BRAM/DDR/QSPI
;REMAP register value e.g. 0-BRAM. 1-QSPI
;HDMI interface is supported
;HDMI I2C register address
;LAN LAN9220 interface is supported
;LAN LAN9220 base address
;RTC PL031 interface is supported
;RTC PL031 base address
;QSPI interface is supported
Copyright © 2017–2020 Arm Limited or its affiliates. All rights
reserved.
Non-Confidential
files that the MCC loads into external memory during
board.txt
OSCCLK[0]
- refclk
- ACLK
- MCLK
- GPUCLK
- AUDCLK
- HDLCD (MCC overrides this value)
3 Configuration
3.5 Configuration files
file.
file.
.txt
3-65
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