Reset, Powerup, And Configuration - ARM MPS3 Technical Reference Manual

2.4

Reset, powerup, and configuration

The MPS3 board provides five external resets to the FPGA.
Overview of reset system
The MPS3 board provides a hardware reset, and a software reset.
There are two hardware reset buttons. They perform the same function and both are labeled PBRST.
Pressing one of them puts the system into the standby state.
There are two On/Off soft reset buttons. Both are labeled PBON. Pressing one of them performs a
software reset, or if the board is already in the standby state, powers up the system.
The following figure shows the MPS3 board reset system, where the FPGA contains a user image.
CB_nPOR CB_nRST FPGA_nRST
FPGA resets
FPGA_nRST
CB_nPOR
nTRST
CB_nRST, nSRST
100765_0000_04_en
FPGA
User image
MCC
Board and FPGA reset including FPGA PLLs.
The main powerup reset for the FPGA image logic. If a System Control Processor (SCP) is
present in the design, releasing this reset might also trigger the powerup reset sequencing.
Resets the CoreSight DAP.
CB_nRST is the core reset. These inputs are ANDed together in the FPGA. They initiate
operation of the processors and enable the debug tools to debug the processors before they leave
reset.
Copyright © 2017–2020 Arm Limited or its affiliates. All rights
Debug
SCC
SCC CB_CFGnRST
GPIO
nRST
MPS3 FPGA Prototyping Board
reserved.
Non-Confidential
2 Hardware description
2.4 Reset, powerup, and configuration
JTAG
nTRST
nSRST
EN Fixed PSUs
EN Fixed PSUs
Reset logic
MCC reset
PBRST PBON
Hardware On/Off Soft
reset push reset push
buttons buttons
Figure 2-4 MPS3 board reset system
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