Design Settings For Correct Board Operation With A Minimal Design - ARM MPS3 Technical Reference Manual

2.19

Design settings for correct board operation with a minimal design

For correct operation with a minimal design, the MPS3 board requires a minimum amount of RTL in the
FPGA, and certain variable settings in the
Minimum RTL
Configuration file settings
100765_0000_04_en
The following table shows the signals that you must tie off in the FPGA to generate the
minimum RTL for correct operation of the MPS3 board.
If the design does not implement the Serial Configuration Controller (SCC), you must set the
variable FPGA_SCC to FALSE in the board
If the design does not implement the MCC‑SMC interface, you must set the variable
FPGA_SMB to FALSE in the board
See 3.5.2 config.txt generic board configuration file on page
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2.19 Design settings for correct board operation with a minimal design
file.
config.txt
Table 2-3 Minimum RTL for correct operation of the MPS3 board
config.txt
file.
config.txt
reserved.
Non-Confidential
2 Hardware description
FPGA signal Minimum RTL
MMB_IDCLK Tie LOW
EMMC_CLK Tie LOW
QSPI_nCS Tie HIGH
QSPI_SCLK Tie LOW
IOFPGA_SYSWDT Tie LOW
WDOG_RREQ Tie LOW
SMBM_nWAIT Tie HIGH
CFG_DATAOUT Tie LOW
file.
3-64.
2-53