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ARM Express µATX V2M-P1 Technical Reference Manual

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ARM
Motherboard Express µATX
®
V2M-P1
Technical Reference Manual
Copyright © 2009-2014, ARM. All rights reserved.
ARM DUI 0447J (ID052914)

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Summary of Contents for ARM Express µATX V2M-P1

  • Page 1 Motherboard Express µATX ® V2M-P1 Technical Reference Manual Copyright © 2009-2014, ARM. All rights reserved. ARM DUI 0447J (ID052914)
  • Page 2 This document is intended only to assist the reader in the use of the product. ARM shall not be liable for any loss or damage arising from the use of any information in this document, or any error or omission in such information, or any incorrect use of the product.
  • Page 3 • consult the dealer or an experienced radio/TV technician for help. Note It is recommended that wherever possible shielded interface cables be used. ARM DUI 0447J Copyright © 2009-2014, ARM. All rights reserved. ID052914 Non-Confidential...

  • Page 4: Table Of Contents

    Chapter 3 Configuration Configuration environment ..................3-2 Chapter 4 Programmers Model About this programmers model ................4-2 Memory maps ......................4-3 Register summary ....................4-8 Register descriptions ..................... 4-10 ARM DUI 0447J Copyright © 2009-2014, ARM. All rights reserved. ID052914 Non-Confidential...
  • Page 5 IO Peripherals and interfaces ................4-26 Appendix A Signal Descriptions Audio CODEC interface ................... A-2 UART interface ......................A-3 Appendix B Specifications Timing specifications ....................B-2 Electrical Specification ..................... B-7 Appendix C Revisions ARM DUI 0447J Copyright © 2009-2014, ARM. All rights reserved. ID052914 Non-Confidential...

  • Page 6: Preface

    Preface This Technical Reference Manual (TRM) is for the Motherboard Express µATX. It contains the following sections: • About this book on page vii • Feedback on page ARM DUI 0447J Copyright © 2009-2014, ARM. All rights reserved. ID052914 Non-Confidential...

  • Page 7: About This Book

    Glossary The ARM Glossary is a list of terms used in ARM documentation, together with definitions for those terms. The ARM Glossary does not contain terms that are industry standard unless the ARM meaning differs from the generally accepted meaning.
  • Page 8 The actual level is unimportant and does not affect normal operation. Clock HIGH to LOW Transient HIGH/LOW to HIGH Bus stable Bus to high impedance Bus change High impedance to stable bus Key to timing diagram conventions ARM DUI 0447J Copyright © 2009-2014, ARM. All rights reserved. viii ID052914 Non-Confidential...
  • Page 9 ® ARM publications This book contains information that is specific to this product. The following publications are open access documents that provide information about ARM Systems IP peripherals and controllers used in the motherboard: • PrimeCell PS2 Keyboard/Mouse Interface (PL050) Technical Reference Manual ®...
  • Page 10 Preface The following publications provide information about related ARM products and toolkits: • CoreTile Express A9x4 Technical Reference Manual (ARM DUI 0448) ® • CoreTile Express A5x2 Technical Reference Manual (ARM DUI 0541) ® • CoreTile Express A15x2 Technical Reference Manual (ARM DUI 0604) ®...

  • Page 11: Feedback

    Preface Feedback ARM welcomes feedback on this product and its documentation. Feedback on this product If you have any comments or suggestions about this product, contact your supplier and give: • The product name. • The product revision or version.

  • Page 12: Chapter 1 Introduction

    Chapter 1 Introduction This chapter introduces the Motherboard Express µATX. It contains the following sections: • About the Motherboard Express µATX on page 1-2 • Precautions on page 1-5. ARM DUI 0447J Copyright © 2009-2014, ARM. All rights reserved. ID052914 Non-Confidential...

  • Page 13: About The Motherboard Express Μatx

    Uses either a 12V power-supply unit or an external ATX power supply. • Supports LogicTile and CoreTile daughterboards to provide custom peripherals, or early access to ARM core or cluster designs, or production test chips. Supports test chips with an IO voltage range of 0.8-3.3 volts. Figure 1-1 on page 1-3 shows the layout of the motherboard with the JTAG cable to the CoreTile Express JTAG connector and the enclosure power cable to the ATX connector.
  • Page 14 LEDs 5VOK 3.3VOK Micro SDCard Battery CoreTile Express LogicTile Express ATX PSU connector (configuration (MCC daughterboard daughterboard (with plug from memory) RTCC) enclosure connector) Figure 1-1 Motherboard layout ARM DUI 0447J Copyright © 2009-2014, ARM. All rights reserved. ID052914 Non-Confidential...

  • Page 15: Back Panel Connectors

    You can use both push buttons to put the system into Standby State, but only the ON/OFF button can power up the system. For more information, see Power up, on/off and reset signals on page 2-6. ARM DUI 0447J Copyright © 2009-2014, ARM. All rights reserved. ID052914 Non-Confidential...

  • Page 16: Precautions

    Do not remove the board from its enclosure. Caution Do not use near equipment that is: • Sensitive to electromagnetic emissions, for example medical equipment. • A transmitter of electromagnetic emissions. ARM DUI 0447J Copyright © 2009-2014, ARM. All rights reserved. ID052914 Non-Confidential...

  • Page 17: Hardware Description

    Peripherals and interfaces on the motherboard on page 2-12 • Interrupt signals on page 2-18 • DMA signals on page 2-20 • JTAG and test connectors on page 2-21. ARM DUI 0447J Copyright © 2009-2014, ARM. All rights reserved. ID052914 Non-Confidential...

  • Page 18: Motherboard Architecture And Buses

    Multiplex FPGA that selects the source for the audio and video signals to the DVI connector. • Two daughterboard slots, one for a CoreTile Express board and one for LogicTile Express board. ARM DUI 0447J Copyright © 2009-2014, ARM. All rights reserved. ID052914 Non-Confidential...
  • Page 19 ON/OFF/Soft Reset and Hardware RESET push buttons and Power and Status LEDs. • 2 x 64MB of user NOR Flash. • 32MB of user SRAM. • 8MB of local Video SRAM. ARM DUI 0447J Copyright © 2009-2014, ARM. All rights reserved. ID052914 Non-Confidential...
  • Page 20 Video with 25 to 165MHz pixel clock, DTV 480p to 1080p, or PC 640x480 to 1600x1200, VGA to UXGA • Audio S/PDIF interface with 2 channels at 192kHz or I2S interface with eight channels at 96kHz. ARM DUI 0447J Copyright © 2009-2014, ARM. All rights reserved. ID052914 Non-Confidential...
  • Page 21 Note The V2M-P1 motherboard supports a root complex either on the daughterboard in Site 1 or the daughterboard in Site 2. By default the daughterboard in Site 1 is the root complex. The V2M-P1 motherboard does not support an endpoint on either daughterboard.

  • Page 22: Power Up, On/Off And Reset Signals

    See also the ARM Versatile Express Configuration Technical Reference Manual for an ® ™ overview of the startup sequence and the operation of the ON/OFF/Soft Reset and Hardware Reset push-button switches. ARM DUI 0447J Copyright © 2009-2014, ARM. All rights reserved. ID052914 Non-Confidential...
  • Page 23 You can reset the system by briefly pressing the ON/OFF/Soft Reset switch on the back panel. This performs a software reset of the ARM test chip on the CoreTile daughterboard. The MCC and Daughterboard Configuration Controller reset the devices in the system, but do not perform a full re-initialization: The reset switch is briefly pressed and the MCC starts a reset sequence.
  • Page 24 MCC releases CB_nRST. The daughterboards enter the run state. Note No daughterboard configuration files are read as a result of an external JTAG reset. No daughterboard re-configuration is performed. ARM DUI 0447J Copyright © 2009-2014, ARM. All rights reserved. ID052914 Non-Confidential...

  • Page 25: Clock Architecture

    Ensure that the clock settings are within the permitted range. You can configure the motherboard OSC clocks in the following ways: By editing the file. ARM recommends that you perform this method first. board.txt By using of the command from the DEBUG submenu of the MCC command line CFG W in run mode.
  • Page 26 Figure 2-3 Overview of system clocks Note SB_GCLK A divide by two block inside the MUX FPGA derives the 12MHz for the attached CoreTile and LogicTile daughterboards. ARM DUI 0447J Copyright © 2009-2014, ARM. All rights reserved. 2-10 ID052914 Non-Confidential...

  • Page 27: Power

    When power is applied, the system is reconfigured based on the contents of the USBMSD flash memory. See the ARM Versatile Express Configuration Technical Reference Manual. ® ™ ARM DUI 0447J Copyright © 2009-2014, ARM. All rights reserved. 2-11 ID052914 Non-Confidential...

  • Page 28: Peripherals And Interfaces On The Motherboard

    PL050 PrimeCells incorporated into the FPGA. See Keyboard and Mouse Interface, KMI on page 4-32. SD/MMC memory cards An ARM PL180 PrimeCell MCI provides the interface to a MultiMedia Card (MMC) or Secure Digital (SD) card. See MultiMedia Card Interface, MCI on page 4-32.
  • Page 29 User Switch Register on page 4-10 LED Register on page 4-11. Watchdog The ARM SP805 Watchdog module can apply a reset to a system in the event of a software failure. See Watchdog on page 4-40. Figure 2-4 shows the IO interfaces using the ARM Legacy memory map, see...
  • Page 30 4 x UART User LEDS PCIe I2C I/O FPGA Figure 2-5 Architectural block diagram of IO FPGA using the ARM Cortex-A Series memory map 2.5.2 Ethernet The Ethernet interface is implemented using a SMCS LAN9118 10/100 Ethernet controller. The LAN9118 incorporates a Media ACcess (MAC) Layer, a PHYsical (PHY) layer, Host Bus Interface (HBI), receive and transmit FIFOs, power management controls, and a serial configuration EEPROM interface.
  • Page 31 Figure 2-6 MMB multiplexer block diagram 2.5.5 PCI-Express The motherboard supports four PCI-Express slots, of connector widths x4, x4, x8, and x16, each of lane width four. ARM DUI 0447J Copyright © 2009-2014, ARM. All rights reserved. 2-15 ID052914 Non-Confidential...
  • Page 32 PCI-Express root complex. Note The V2M-P1 motherboard supports a root complex either on the daughterboard in Site 1 or on the daughterboard in Site 2. You select which site contains the root complex by editing the file.
  • Page 33 6 ports IO FPGA Serial bus interface Reset and configuration logic Resets Motherboard Configuration Controller (MCC) Motherboard Express μATX Figure 2-7 PCIe bus architecture on the motherboard ARM DUI 0447J Copyright © 2009-2014, ARM. All rights reserved. 2-17 ID052914 Non-Confidential...

  • Page 34: Interrupt Signals

    Table 2-2 Interrupt signals SB_IRQ[ ] interrupt Interrupt signal Description WDOG0INT Watchdog timer SWINT Software interrupt, see Miscellaneous Flags Register on page 4-16 TIM01INT Timer interrupt TIM23INT Timer interrupt ARM DUI 0447J Copyright © 2009-2014, ARM. All rights reserved. 2-18 ID052914 Non-Confidential...
  • Page 35 SB2_INT[3:0] Copy of interrupts SB_IRQ[39:36] [31:26] Reserved [35:32] SB1_INT[3:0] Reserved, interrupts INT[3:0] from Site 1 daughterboard [39:36] SB2_INT[3:0] Reserved, interrupts INT[3:0] from Site 2 daughterboard [47:40] Reserved ARM DUI 0447J Copyright © 2009-2014, ARM. All rights reserved. 2-19 ID052914 Non-Confidential...

  • Page 36: Dma Signals

    (in Site 1) SB_nDRQ[7:2] SB_nDRQ[7:2] SB_nDACK[7:2] SB_nDACK[7:2] FPGA Test chip SB_nDRQ[1:0] SB_nDRQ[1:0] SB_nDACK[1:0] SB_nDACK[1:0] HDRY HDRY HDRY1 HDRY2 SB_nDRQ[1:0] SB_nDACK[1:0] IO FPGA Motherboard Express μATX Figure 2-9 DMA architecture ARM DUI 0447J Copyright © 2009-2014, ARM. All rights reserved. 2-20 ID052914 Non-Confidential...

  • Page 37: Jtag And Test Connectors

    Hardware Description JTAG and test connectors The motherboard is not equipped with an ARM debug JTAG connector. To debug the application code, connect a debugger to the JTAG connector on the CoreTile Express daughterboard. Note For convenience, you can connect the JTAG connector on the CoreTile Express daughterboard to the JTAG connector on the back panel.

  • Page 38: Configuration

    Chapter 3 Configuration This chapter describes the configuration sequence for the Motherboard Express µATX and any attached daughterboards. It contains the following section: • Configuration environment on page 3-2. ARM DUI 0447J Copyright © 2009-2014, ARM. All rights reserved. ID052914 Non-Confidential...

  • Page 39: Configuration Environment

    Motherboard Express (V2M-P1) Figure 3-1 Configuration architecture The configuration environment consists of the following hardware components: • Motherboard Configuration Controller (MCC) on the Motherboard Express, V2M-P1. • Daughterboard Configuration Controller on the CoreTile Express daughterboard and on the LogicTile Express daughterboard.
  • Page 40 • Configuration EEPROM on the CoreTile Express daughterboard and on the LogicTile Express daughterboard. • HDRY headers on the Motherboard Express, V2M-P1, CoreTile Express and LogicTile Express daughterboards. See the ARM Versatile Express Configuration Technical Reference Manual and the Technical ®...
  • Page 41 About this programmers model on page 4-2 • Memory maps on page 4-3 • Register summary on page 4-8 • Register descriptions on page 4-10 • IO Peripherals and interfaces on page 4-26. ARM DUI 0447J Copyright © 2009-2014, ARM. All rights reserved. ID052914 Non-Confidential...

  • Page 42: About This Programmers Model

    All register bits are reset to a logic 0 by a system or power-on reset. • Access type in Table 4-3 on page 4-8 is described as follows: Read and write. Read only. Write only. ARM DUI 0447J Copyright © 2009-2014, ARM. All rights reserved. ID052914 Non-Confidential...

  • Page 43: Memory Maps

    Programmers Model Memory maps The memory map details depend on whether the daughterboard uses the ARM Legacy memory map or the ARM Cortex-A Series memory map. 4.2.1 ARM Legacy memory map Figure 4-1 shows an example of the Legacy system memory map when the motherboard is used with the CoreTile Express A9x4 daughterboard.
  • Page 44 Programmers Model Table 4-1 shows the peripherals and memory on the motherboard using the ARM legacy memory map. The addresses are offsets from the base addresses of the SMB chip selects. Table 4-1 Motherboard peripheral ARM legacy memory map Peripheral...
  • Page 45 (SMB CS0 to CS6) 0x00000000 0x00000000 = CS0 Figure 4-2 ARM Cortex-A Series system memory map as viewed from a CoreTile Express A5x2 daughterboard Caution The attached daughterboard defines the address ranges for the SMB chip selects. ARM DUI 0447J Copyright ©...
  • Page 46 Programmers Model Table 4-2 shows the peripherals and memory on the motherboard when using the ARM Cortex-A Series memory map. The addresses are offsets are from the base addresses of the SMB chip selects. Table 4-2 Motherboard peripheral ARM Cortex-A Series memory map...
  • Page 47 Programmers Model Table 4-2 Motherboard peripheral ARM Cortex-A Series memory map (continued) Peripheral Interface logic SMB chip select Address offset Reserved 0x00150000 0x0015FFFF Serial Bus DVI Custom 0x00160000 0x0016FFFF ARM PL031 0x00170000 0x0017FFFF Reserved 0x00180000 0x0018FFFF Reserved 0x00190000 0x0019FFFF Compact Flash...

  • Page 48: Register Summary

    The following information applies to the Motherboard Express uATX registers: • If your daughterboard uses the ARM Legacy memory map, the system register addresses are offsets from the SMB CS7 base address and this depends on the mapping in the daughterboard.
  • Page 49 0x00000000 0x0FFF a. Where the register contains both Read Only and Read Write bits, see register. b. Where = unknown at reset, or depending on build, see register. ARM DUI 0447J Copyright © 2009-2014, ARM. All rights reserved. ID052914 Non-Confidential...

  • Page 50: Register Descriptions

    Purpose Reads the entry in the file. A value of 1 indicates USERSWITCH config.txt that the switch is on. Usage constraints See Table 4-5 on page 4-11. ARM DUI 0447J Copyright © 2009-2014, ARM. All rights reserved. 4-10 ID052914 Non-Confidential...
  • Page 51 Controls the user LEDs on the motherboard. At reset, all LEDs are turned off. The Boot Monitor updates the LED value. Usage constraints There are no usage constraints. Configurations Available in all configurations. Attributes Table 4-3 on page 4-8. ARM DUI 0447J Copyright © 2009-2014, ARM. All rights reserved. 4-11 ID052914 Non-Confidential...
  • Page 52 Provides two 32-bit register locations containing general-purpose flags. You can assign any meaning to the flags. Usage constraints There are no usage constraints. Configurations Available in all configurations. Attributes Table 4-3 on page 4-8. ARM DUI 0447J Copyright © 2009-2014, ARM. All rights reserved. 4-12 ID052914 Non-Confidential...
  • Page 53 Usage constraints There are no usage constraints. Configurations Available in all configurations. Attributes Table 4-3 on page 4-8. Figure 4-6 on page 4-14 shows the bit assignments. ARM DUI 0447J Copyright © 2009-2014, ARM. All rights reserved. 4-13 ID052914 Non-Confidential...
  • Page 54 Usage constraints There are no usage constraints. Configurations Available in all configurations. Attributes Table 4-3 on page 4-8. Figure 4-7 shows the bit assignments. Undefined FLASHWPn Figure 4-7 SYS_FLASH Register bit assignments ARM DUI 0447J Copyright © 2009-2014, ARM. All rights reserved. 4-14 ID052914 Non-Confidential...
  • Page 55 User applications can read these switch settings. CONFIGSWITCH in the file. config.txt See the ARM Versatile Express Boot Monitor ® ™ Reference Manual for more switch settings. ARM DUI 0447J Copyright © 2009-2014, ARM. All rights reserved. 4-15 ID052914 Non-Confidential...
  • Page 56 14 13 20 19 Undefined Undefined Undefined SB_EVENTI nDBDET1 for site1 USBnOEN[1:0] nDBDET2 for site2 USB_SUSPEND[1:0] MASTERSITE NOR select SB1/SB2_EVENTO [1:0] SWINT Figure 4-9 SYS_MISC Register bit assignments ARM DUI 0447J Copyright © 2009-2014, ARM. All rights reserved. 4-16 ID052914 Non-Confidential...
  • Page 57 DMA mapping is disabled by default. There is no DMA controller in the motherboard. See Figure 2-9 on page 2-20. Usage constraints There are no usage constraints. Configurations Available in all configurations. Attributes Table 4-3 on page 4-8. ARM DUI 0447J Copyright © 2009-2014, ARM. All rights reserved. 4-17 ID052914 Non-Confidential...
  • Page 58 4-8. Figure 4-11 shows the bit assignments. 24 23 16 15 12 11 BOARD BOARD PROC_ID0 Undefined HBI number REVISION VARIANT Figure 4-11 SYS_PROCID0 Register bit assignments ARM DUI 0447J Copyright © 2009-2014, ARM. All rights reserved. 4-18 ID052914 Non-Confidential...
  • Page 59 As an example, the CoreTile Express daughterboard has a reset value of 0x0C000191 4.4.13 SYS_PRODCID1 Register The SYS_PRODCID1 Register characteristics are: Purpose Indicates the ARM core or cluster type at the LogicTile Express Site 2. ARM DUI 0447J Copyright © 2009-2014, ARM. All rights reserved. 4-19 ID052914 Non-Confidential...
  • Page 60 0x191 LogicTile Express 3MG (V2F-1XV5). 0x192 LogicTile Express 13MG (V2F-1XV5). 0x217 CoreTile Express A5x2 (V2P-CA5s). 0x225 CoreTile Express A15x2 (V2P-CA15). 0x237 CoreTile Express A15x2 A7x3 (V2P-CA15_A7). 0x249 ARM DUI 0447J Copyright © 2009-2014, ARM. All rights reserved. 4-20 ID052914 Non-Confidential...
  • Page 61 Table 4-3 on page 4-8. Table 4-17 shows the register bit assignments. Table 4-17 SYS_CFGDATA Register bit assignments Bits Name Description [31:0] CFG data 32-bit configuration data register ARM DUI 0447J Copyright © 2009-2014, ARM. All rights reserved. 4-21 ID052914 Non-Confidential...
  • Page 62 Programmers Model Note The same interface is accessible from the MCC command line. See the ARM Versatile Express ® ™ Configuration Technical Reference Manual CFG command. Configuration Control Register The SYS_CFGCTRL Register characteristics are: Purpose Controls the transfer of data across the SPI interface between the MCC and a Daughterboard Configuration Controller.
  • Page 63 3-bit DVI mode value VGA-UXGA VGA. b000 SVGA. b001 XGA. b010 SXGA. b011 UXGA. b100 SYS_CFG_POWER Power, µW 1µW-4.3kW Power value SYS_CFG_ENERGY Energy, µJ 1µJ-2^64µJ On-board energy meter ARM DUI 0447J Copyright © 2009-2014, ARM. All rights reserved. 4-23 ID052914 Non-Confidential...
  • Page 64 // wait for complete flag to be set while (!(SYS_CFGSTAT & SYS_CFG_COMPLETE) // check error status and return error flag if set if (SYS_CFGSTAT & SYS_CFG_ERROR) return FAILURE ARM DUI 0447J Copyright © 2009-2014, ARM. All rights reserved. 4-24 ID052914 Non-Confidential...
  • Page 65 (!(SYS_CFGSTAT & SYS_CFG_COMPLETE)) // check error status flag and return error flag if set if (SYS_CFGSTAT & SYS_CFG_ERROR) return FAILURE else // read data data = SYS_CFGDATA return SUCCESS ARM DUI 0447J Copyright © 2009-2014, ARM. All rights reserved. 4-25 ID052914 Non-Confidential...

  • Page 66: Io Peripherals And Interfaces

    Interrupt DMA mapping Table 4-14 on page 4-18. Release version ARM AACI PL041 r0p0, modified to one channel and 256 FIFO depth in compact mode, and 512 FIFO depth in non-compact mode. Platform Library support No support provided. Reference documentation PrimeCell Advanced Audio CODEC Interface (PL041) Technical Reference Manual and National ®...
  • Page 67 Color LCD Controller The motherboard PL111 PrimeCell Color LCD Controller (CLCDC) is an AMBA-compliant SoC peripheral that is developed, tested, and licensed by ARM. The CoreTile Express daughterboard typically has a higher-performance CLCD controller. This controller is in the IO FPGA and is intended for use with daughterboards that do not contain their own CLCD controller.
  • Page 68 OSCCLK1, 23.75MHz default, is assigned as CLCDCLK for the LCD controller. The Post Screen has a 640x480 VGA 8-bit color pallet. Default display resolution is 1024x768 at a 60Hz frame rate. The default color depth is 16-bit. See the ARM PrimeCell Color ®...
  • Page 69 If your daughterboard uses the ARM Legacy memory map the CompactFlash control register is at SMB CS7 base address + 0x1A000 If your daughterboard uses the ARM Cortex-A Series memory map the CompactFlash control register is at SMB CS3 base address + 0x1A0000 Note See the Technical Reference Manual for your daughterboard.
  • Page 70 The registers map onto the CS7 chip select. • Cortex-A Series memory map: — The registers map onto the CS3 chip select. Note See the Technical Reference Manual for your daughterboard. ARM DUI 0447J Copyright © 2009-2014, ARM. All rights reserved. 4-30 ID052914 Non-Confidential...
  • Page 71 See the LAN9118 data sheet or the self-test program supplied on the Versatile Express DVD for additional information. When manufactured, ARM values for the Ethernet MAC address and the register base address are loaded into the EEPROM. The register base address is 0 and the unique MAC address is displayed on a sticker on the motherboard.
  • Page 72 Programmers Model 4.5.5 Keyboard and Mouse Interface, KMI The PL050 PrimeCell PS2 Keyboard/Mouse Interface (KMI) is an AMBA-compliant SoC peripheral that is developed, tested, and licensed by ARM. Two KMIs are present on the motherboard: KMI0 Used for keyboard input.
  • Page 73 Real Time Clock, RTC The PL031 PrimeCell Real Time Clock Controller (RTC) is an AMBA-compliant SoC peripheral that is developed, tested, and licensed by ARM. A counter in the RTC is incremented every second. The RTC can therefore be used as a basic alarm function or long time-base counter.
  • Page 74 The registers map onto the CS7 chip select. • Cortex-A Series memory map: — The registers map onto the CS3 chip select. Note See the Technical Reference Manual for your daughterboard. ARM DUI 0447J Copyright © 2009-2014, ARM. All rights reserved. 4-34 ID052914 Non-Confidential...
  • Page 75 SB_CONTROLC Write Clear serial control bits: — CS7 + Bit [0] is SCL 0x00002004 • Cortex-A Series memory map: Bit [1] is SDA — CS3 + 0x00002004 ARM DUI 0447J Copyright © 2009-2014, ARM. All rights reserved. 4-35 ID052914 Non-Confidential...
  • Page 76 The registers map onto the CS7 chip select. • Cortex-A Series memory map: — The registers map onto the CS3 chip select. Note See the Technical Reference Manual for your daughterboard. ARM DUI 0447J Copyright © 2009-2014, ARM. All rights reserved. 4-36 ID052914 Non-Confidential...
  • Page 77 4.5.10 UART The PL011 PrimeCell UART is an AMBA-compliant SoC peripheral that is developed, tested, and licensed by ARM. The 24MHz reference clock to the UARTs is from the crystal oscillator that is part of OSCCLK2 The internal registers of the UART peripheral are memory-mapped onto a static memory bus chip select.
  • Page 78 The PrimeCell UART varies from the industry-standard 16C550 UART device as follows: • UART0 has full handshaking signals, RTS, CTS, DSR, DTR, DCD, and RI, but DSR and CTS are used for remote operation. See the ARM Versatile Express Configuration ®...
  • Page 79 SMB CS2 base address + 0x03000000 Interrupt None Release version Custom interface to external controller Reference documentation ISP1761 Hi-Speed Universal Serial Bus On-The-Go controller Product data sheet ARM DUI 0447J Copyright © 2009-2014, ARM. All rights reserved. 4-39 ID052914 Non-Confidential...
  • Page 80 The chip select that they map onto depends on the memory map your daughterboard is using as follows: • ARM legacy memory map: — The registers map onto the CS7 chip select. ARM DUI 0447J Copyright © 2009-2014, ARM. All rights reserved. 4-40 ID052914 Non-Confidential...
  • Page 81 Platform Library support No support provided. Reference documentation Watchdog Module (SP805) Technical Reference Manual. ® Note The Watchdog counter is disabled if the core is in debug state. ARM DUI 0447J Copyright © 2009-2014, ARM. All rights reserved. 4-41 ID052914 Non-Confidential...

  • Page 82: Appendix A Signal Descriptions

    • Audio CODEC interface on page A-2 • UART interface on page A-3. Note This appendix only covers non-standard connectors or non-standard signal connections to an industry-standard connector. ARM DUI 0447J Copyright © 2009-2014, ARM. All rights reserved. ID052914 Non-Confidential...

  • Page 83: Audio Codec Interface

    AGND CODEC_LINE_IN_L AGND Line in AGND CODEC_LINE_IN_R AGND AMP_L Line out AMP_R AGND CODEC_MIC2 AGND Mic in AGND CODEC_MIC1 Figure A-1 Audio connectors ARM DUI 0447J Copyright © 2009-2014, ARM. All rights reserved. ID052914 Non-Confidential...

  • Page 84: Uart Interface

    UART interface The motherboard provides four serial transceivers on the rear panel of the enclosure. Figure A-2 shows the pin numbering for the 9-pin D-type male connector used on the V2M-P1 Table A-1 shows the signal assignment for the connectors.

  • Page 85: Appendix B Specifications

    Appendix B Specifications This appendix contains the specification for the motherboard. It contains the following sections: • Timing specifications on page B-2 • Electrical Specification on page B-7. ARM DUI 0447J Copyright © 2009-2014, ARM. All rights reserved. ID052914 Non-Confidential...

  • Page 86: Timing Specifications

    = 5 cycles, minimum. Trc_ncs7 • = 7 cycles, minimum. Trc_ncs3 All signals are clocked off SMB_CLKO. SMB_CLKI is transmitted by the IO FPGA, but it does not clock any data. ARM DUI 0447J Copyright © 2009-2014, ARM. All rights reserved. ID052914 Non-Confidential...
  • Page 87 = 5 cycles, minimum. Trc_ncs7 • = 7 cycles, minimum. Trc_ncs3 All signals are clocked off SMB_CLKO. SMB_CLKI is transmitted by the IO FPGA, but it does not clock any data. ARM DUI 0447J Copyright © 2009-2014, ARM. All rights reserved. ID052914 Non-Confidential...
  • Page 88 FPGA and an additional 2 clocks for the read data to be passed back. The total delay is 3.5 clock cycles. B.1.4 SMB asynchronous write Figure B-4 on page B-5 shows the asynchronous write timing. ARM DUI 0447J Copyright © 2009-2014, ARM. All rights reserved. ID052914 Non-Confidential...
  • Page 89 An asynchronous write therefore has a penalty of 1.5 clock cycles because of going though the IO FPGA. B.1.5 Video multiplexer FPGA timing Figure B-5 on page B-6 shows the video multiplexer FPGA timing. ARM DUI 0447J Copyright © 2009-2014, ARM. All rights reserved. ID052914 Non-Confidential...
  • Page 90 • Audio data, clocked by MMB_MCLK — Tis = 5.30ns. — Tih = 0.00ns. • Audio data, clocked by MMB_SCLK — Tis = 2.65ns. — Tih = 0.00ns. ARM DUI 0447J Copyright © 2009-2014, ARM. All rights reserved. ID052914 Non-Confidential...

  • Page 91: Electrical Specification

    IO voltage to motherboard Note You can stack up to eight daughterboards in each site of the V2M-P1 motherboard. Although the 3V3 voltage regulator can supply 1A to each stack, ARM recommends that each daughterboard draws only 100mA to give each stack a 200mA safety margin.
  • Page 92 Table 4-1 on page 4-4. All versions. SRAM, Ethernet and USB, in the motherboard memory map. Added description of the SYS_CFGSW register. Table 4-11 on page 4-15. Version B. ARM DUI 0447J Copyright © 2009-2014, ARM. All rights reserved. ID052914 Non-Confidential...
  • Page 93 Table added to 100Hz Counter Register. Table 4-7 on page 4-12. All versions. SYS_PROCID0 and SYS_PROCID1 Register bit assignments Figure 4-11 on page 4-18 All versions. figures updated. Figure 4-12 on page 4-20. ARM DUI 0447J Copyright © 2009-2014, ARM. All rights reserved. ID052914 Non-Confidential...
  • Page 94 Debug commands table updated for more than one Table 3-4 on page 3-18. All versions. Daughterboard Configuration Controller device. MMCI interface logic description corrected to ARM PL180 in Table 4-1 on page 4-4. All versions. table. SYS_MISC Register bit assignments figure and table updated Figure 4-9 on page 4-16 All versions.
  • Page 95 Text references, diagrams, and new diagrams added to Figure 2-4 on page 2-13 All versions. include the new memory map, the ARM Cortex-A Series Figure 2-5 on page 2-14 memory map. Existing references to existing memory Memory maps on page 4-3 map changed to ARM legacy memory map.
  • Page 96 Updates to Advanced Audio CODEC Interface description. Table 4-21 on page 4-26 All versions. Table 4-22 on page 4-27. Glossary removed. Reference and link to ARM Glossary added Glossary on page vii All versions. to Preface. ARM DUI 0447J Copyright © 2009-2014, ARM. All rights reserved.
  • Page 97 Table C-6 Differences between Issue E and Issue F (continued) Change Location Affects Configuration chapter shortened. Chapter 3 Configuration All versions. Information is now in a new document the ARM Versatile ® ™ Express Configuration Technical Reference Manual. Changes cross-references to configuration and reset Chapter 2 Hardware Description All versions.
  • Page 98 By default, the root complex is on the daughterboard in Site 1. The motherboard does not support an endpoint on either daughterboard. ARM DUI 0447J Copyright © 2009-2014, ARM. All rights reserved. ID052914 Non-Confidential...

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