Fpga Ddr4 Memory Interface - ARM MPS3 Technical Reference Manual

2.14

FPGA DDR4 memory interface

The MPS3 board provides 4GB of DDR4 SODIMM and a DDR4 interface to the FPGA.
The DDR4 controller and PHY interface uses the Xilinx Memory Interface Generator (MIG). The
interface is 64‑bit and uses 10 byte lanes.
The interface supports up to 900MHz, 1800MT/s, with the supplied SODIMM
(MTA4ATF51264HZ-2GB31).
The following figure shows the FPGA DDR4 memory interface.
AXI MIG
100765_0000_04_en
Kintex XCKU115 FPGA
Byte
Lane 1
Byte
Lane 2
I/O
bank 1
Byte
Lane 3
Byte
Lane 4
Byte
Lane 5
Byte
Lane 6
I/O
bank 2
Byte
Lane 7
Byte
Lane 8
Byte
Lane 9
Byte
Lane 10
I/O
bank 3
Byte
Lane 11
Byte
Lane 12
MPS3 FPGA Prototyping Board
Copyright © 2017–2020 Arm Limited or its affiliates. All rights
I/O
I/O
CK[1:0]
I/O DQ[63:0]
DQS[7:0]
I/O
DM[7:0]
CS[1:0]
I/O
BA[1:0]
I/O
BG[1:0]
ACT
I/O
A[16:0]
I/O CKE[1:0]
ODT[1:0]
I/O
RESET
PARIN
I/O
ALERT
I/O
I/O
Figure 2-18 Kintex XCKU115 FPGA DDR4 memory interface
reserved.
Non-Confidential
2 Hardware description
2.14 FPGA DDR4 memory interface
512MB
Group 0
Bank 1
512MB
Group 1
512MB
Group 0
Bank 2
512MB
Group 1
512MB
Group 0
Bank 3
512MB
Group 1
512MB
Group 0
Bank 4
512MB
Group 1
4GB DDR4
SODIMM
MTA4ATF51264HZ-2G3B1
2-41