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CB_CFGnRST
CPUWAIT
Reset sequence
The following figure shows the MPS3 board reset and powerup timing cycle including board
configuration.
MCC
MCC
reset
config
MCC
reset
PBON/
User ON
CB_VRAMP
FPGA_nRST
CB_CFGnRST
CB_nPOR
CB_nRST
CPUWAIT
(if supported)
nSRST
Related information
1.3 Location of components on the MPS3 board on page 1-15
100765_0000_04_en
The reset signal for the serial interface of the Serial Configuration Controller (SCC).
Core register that is used to release processor core or cores from reset.
Board
and
FPGA
config
Power
(inc
ON
FPGA
PLLs)
Copyright © 2017–2020 Arm Limited or its affiliates. All rights
Subsystem
reset.
Release
SCC
Pre-load
Release
CPU
config
memory
logic
reset
reset.
Figure 2-5 MPS3 board reset and configuration timing
reserved.
Non-Confidential
2 Hardware description
2.4 Reset, powerup, and configuration
Release
Processor
System
processor
boot
running
wait
Warm
reset
2-26
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