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2.10
Audio codec interface
An AACI audio codec on the MPS3 board provides a stereo audio interface with Line In, Line Out, and
Microphone In.
The AACI audio codec and the stereo audio interface enable you to implement an audio codec interface.
The FPGA configures the codec over I
controller that consists of a data buffer and serializer.
The interface supports the standard audio data rate of 48kHz, up to a maximum of 96kHz. The codec
contains audio power amplifiers that can drive up to 500mW, 8Ω stereo speakers.
The audio codec drives the stacked stereo jack on the MPS3 board. When using an electret type of
microphones, use jumpers J58 (L) and J59 (R) to enable microphone bias current.
The following figure shows an audio codec interface example design.
MPS3 FPGA Prototyping Board
Related information
A.8 Audio connectors, stacked stereo jacks on page Appx-A-86
1.3 Location of components on the MPS3 board on page 1-15
100765_0000_04_en
FPGA
APB
I
2
C
I2C1_DAT
AACI_SDOUT
I2C1_CLK
AACI_SDIN
Audio codec
Mic In
Copyright © 2017–2020 Arm Limited or its affiliates. All rights
2
2
C and has an I
S audio interface. The I
I
2
S
AACI_LRCLK
AACI_MCLK
AACI_SCLK
CS42L52
Line Out
Line In
Stacked stereo jack
Figure 2-15 MPS3 board audio codec interface example design
reserved.
Non-Confidential
2 Hardware description
2.10 Audio codec interface
2
S controller is a dedicated
24.576MHz
OSC5
2-37
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