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A.1
Debug connectors
The MPS3 board provides connectors that support P-JTAG processor debug, F-JTAG FPGA debug,
16‑bit and 4‑bit trace, and SWD.
This section contains the following subsections:
•
A.1.1 20-pin IDC connector on page
•
A.1.2 10-pin IDC connector on page
•
A.1.3 20-pin Cortex debug and ETM connector on page
•
A.1.4 38-pin MICTOR connector on page
•
A.1.5 14-pin F-JTAG ILA connector on page
•
A.1.6 Debug USB 2.0 connector on page
A.1.1
20-pin IDC connector
The MPS3 board provides one 1V8 20‑pin IDC connector that supports P‑JTAG processor debug to
enable connection of DSTREAM, or a compatible third‑party debugger. The connector also supports
Serial Wire Debug (SWD).
The 20‑pin IDC connector connects to general‑purpose pins on the FPGA. The availability of P‑JTAG or
SWD depends on the design that you implement in the FPGA.
The following figure shows the 20‑pin IDC connector, J14.
The following table shows the pin mapping for each P‑JTAG and SWD signal on the 20‑pin IDC
connector.
•
Pins 1, 3, 5, 7, 13, 15, and 19 have pullup resistors to 1V8.
•
Pins 9, 11, and 17 have pulldown resistors to GND.
100765_0000_04_en
Note
Copyright © 2017–2020 Arm Limited or its affiliates. All rights
Non-Confidential
Appx-A-71.
Appx-A-72.
Appx-A-72.
Appx-A-73.
Appx-A-74.
Appx-A-75.
2
1
Table A-1 20-pin IDC connector, J14, pin mapping
Pin Signal
1
3
5
7
9
11
13
15
17
19
reserved.
A Signal descriptions
A.1 Debug connectors
Figure A-1 20-pin IDC connector
Pin Signal
1V8_REF
2
1V8
nTRST
4
GND
TDI
6
GND
SWDIO/TMS
8
GND
SWDCLK/TCK 10
GND
GND/RTCK
12
GND
SWO/TDO
14
GND
nSRST
16
GND
NC/DBGRQ
18
GNDDETECT
NC/DBACK
20
GND
20
19
Appx-A-71
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