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WJ-BVlb-iy/rt. nr
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circuit DESCRIPTION
3.4.24.3
Serial Sync I/O Buffers, U1-U3
Buffers U1-U3 are used only when the Sync Serial I/O remote control
mode is operational.
I/O data signals appear from connector Jl and drive the inputs of
each buffer, UlA, U2A and U3A.
These are inverted and passed to UIB, U2B and U3B
respectively. They are once again inverted and passed on to the remote connector on
the rear panel.
The buffer outputs are low impedance and can source or sink
considerable current over long distance lines.
3.4.25
SYNC SERIAL INPUT/OUTPUT (A6A5)
The Sync Serial I/O mounts on the A6 Motherboard (see paragraph 3.3.6).
Refer to Figure 3-32, Sync Serial I/O Block Diagram, as an aid in understanding the
following description.
Figure 6-33, Sync Serial I/O Schematic Diagram, may be
referred to for greater component level detail, if desired.
The Asynchronous I/O
consists of the following major circuit areas:
o
Address Latch ,U9
o
Address Decoders, U7 and UIO
o
Serial to Parallel Converters, U3-U6
3.4.25.1
Address Latch, U9
The address latch is an 8-bit latch which captures and holds an address
from the address/data bus while a specific operation is being performed.
The latch
outputs are used to address the inputs of the address decoders. The microprocessor on
A6A1 outputs an address on the bus and follows by bring the ALE line momentarily
low.
This transfers the address on the bus to the Q outputs of U9.
3.4.25.2
Address Decoders, U7 and UIO
Decoder U7 is used to select multiplexers Ul and U2.
U7 is a 3-to-8 line
decoder. The input is addressed by the address latch. When a valid address is present
at the decoder input, bit A12 on the bus is brought high, activating the addressed
decoder output.
When U7-1 is addressed high, the U7-Y0 output is low, selecting Ul.
When U7-2 is addressed high, the U7-Y1 output is low, selecting U2.
3.4.25.3
Serial to Parallel Converters, U3 to U6
U3 to U6 form a 64-bit shift register.
In typical operation, serial data
pulses (DTR from the controller) are clocked into the SR (pin 11) and out of the Q7
(pin 17) terminals of each shift register.
When all 64 bits have clocked in, the
registers U3-U6 signal the microprocessor via UIO and the address/data bus that they
are full.
The 64 bits are then clocked through multiplexers Ul and U2 (8 bits at a
time) until all 64 bits are transferred to the microprocessor.
3-67
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