Watkins-Johnson Company WJ-8718-19/FE Instruction Manual page 119

CIRCUIT DESCRIPTION WJ-8718-19/FE HF RECEIVER
3.4.13 455 kHz FILTER SWITCH (A4A3) (791595)
The 455 kHz Filter Switch mounts 6n the IF Motherboard, A4, (see
paragraph 3.3.4). Figure 3-18 is a detailed functional block diagram of the 455 kHz
Filter Switch which should be referred to in the following circuit description.
Figure 6-17, 455 kHz Filter Switch Schematic Diagram, may be referred to for greater-
component level detail, if desired.
The 455 kHz Filter Switch receives the 455 kHz IF signal output from the
10.7 MHz/455 kHz Converter, A4A2. The 455 kHz Filter Switch routes the IF signal
through one of two bandpass filters of 1.0 kHz and 0.3 kHz bandwidth, or through a
wideband path which allows the full bandwidth from A3, A4A1 and A4A2 to pass. The
selection of the filter path is made by application of a logic high level to one of the
three control terminals.
The input signal at pin 13 connects in parallel to Ql, Q3, and Q5. When
Ql is biased on, the signal passes through Ql and is fed through the 0.3 kHz crystal
filter (FL1). The biasing of Ql and Q2 is controlled by the voltage on pin 19. When
this voltage is high (+5 V), the output of UID will be +12 V, thus biasing Ql and Q2
When this voltage is low (0 V), the output of UID will be -12 V which will cause an
approximate 1 V reverse bias to the bases of Ql and Q2, and thus they are turned off.
When the 1.0 kHz bandwidth is selected, module pin 17 is high and U1A
rturns on Q3 and Q4. When the 3.2 kHz, 6 kHz or 50 kHz bandwidths are'selected
module pin 15 is high and U1B turns on Q5 and Q6. When ISB, LSB, or USB are
selected, all three control lines to this card are low and all three signal paths are
inhibited.
All transistors, Ql through Q6, are operated as common emitter amplifiers
with unbypassed emitter resistors to control their gain. Through any of the three
signal paths there is a net voltage gain of approximately 9 dB from the input to the
output of the module. OPAMP section U1C is not used and is as shown in the
schematic connected in an inoperative condition.
3.4.14 AGC AMPLIFIER (A4A6) (791675)
The AGC Amplifier mounts on the IF Motherboard, A4, (see paragraph
u ,ViIFlgu/e 3"19 1S a detailed functional block diagram of the AGC Amplifier which
should be referred to in the following circuit description. Figure 6-18, AGC Amplifier
Schematic Diagram, may be referred to for greater component level detail, if desired.
In the AGC module, the direct coupled output of the AM detector is
filtered by R5 and C3 to limit the speed of response of the Fast AGC. In the Fast
AGC Mode, Q7 is biased off, disconnecting C4, so Ql operates simply as an emitter
follower. Q7 is biased on when Slow AGC is selected, grounding the negative end of
C4 Ql continues to be off until C4 is discharged by R3. This action gives the fast
attack response and slow decay response of the Slow AGC mode. Zener diode CR2 acts
as a limiter to prevent short bursts of signal from overcharging C4 (which might cut
^off the amplifiers for many seconds). "
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