Watkins-Johnson Company WJ-8718-19/FE Instruction Manual page 147

CIRCUIT DESCRIPTION WJ-8718-19/FE HF RECEIVER
o UART
o RS-232 Drivers
o Address Latch
o Address Decoder
o Switch Latch
3.4.23.1 UART
The UART, Ul, contains a transmit and a receive section. The receiver
converts the incoming RXD serial stream into 8-bit parallel words and places them on
the Digital Control data bus, AD0-AD7. The transmitter converts parallel words on the
data bus to a serial TXD data stream. Timing and control of receive and transmit
functions is coordinated by the address latch and decoder. The UART is initialized by
the RESET line from the CPU. When received data is present in the UART, the UART
sets the RxRDY line low to interrupt the CPU. A clock generator, U5, is switch
settable, and drives the UART at 16 times the baud rate of the serial data stream.
3.4.23.2 RS-232 Drivers
Drivers U7-U10 convert TTL level signals to bipolar RS-232 levels. U7
interfaces RTS, TXD and DSR signals from Ul to the remote controller. U8 interfaces
DTR, CTS and RXD signals from Ul to the remote controller. U9 interfaces DSR, CTS
and RXD signals from the remote controller to Ul. UIO interfaces RTS, DTR and TXD
signals from the remote controller to Ul.
3.4.23.3 Address Latch
The address latch, U2, is an 8-bit latch which captures and holds an
address present on the AD0-AD7 bus. When a valid address is present at the input of
the latch, the CPU brings the ALE line momentarily low, transferring the address to
the Q outputs of the latch. The QO output selects transmit or receive in the UART.
Q1-Q7 drive the address and enable inputs to the decoder.
3.4.23.4 Address Decoder
The address decoder, U4, is a 3- to 8-line decoder. Its address bits are
driven from the Q1-Q3 outputs of the address latch. Its enable inputs driven from Q4
and Q5 of the latch and the A12 from the address bus. The YO output enables the
UART, while the Yl output enables the switch latch.
3.4.23.5 Switch Latch
The switch latch, U3, is an 8-bit latch which reads the status of the
programming switch, S2. The setting of the 8 switch in S2 is latched through the
switch latch by the Yl decoder output. The switch latch output is placed on the data
bus, AD0-AD7, and is read by the CPU.
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