Watkins-Johnson Company WJ-8718-19/FE Instruction Manual page 143

CIRCUIT DESCRIPTION WJ-8718-19/FE HF RECEIVER
3.4.21.6 Frequency Registers
Frequency registers U12 through U17 are octal D-type flip-flops. These
registers latch bus data to the synthesizer circuits. The clock input of each register
is tied to a Y output from U8. When addressed by the microprocessor, one of the U8
Y outputs goes low, clocking its respective frequency register. This causes the data
present on the bus to be clocked through the D input of the register to its Q output.
3.4.22 IF INTERFACE (A6A2)
The IF Interface mounts on the I/O Motherboard, A6 (see paragraph 3.3.6).
The IF Interface interfaces the Digital Control microprocessor with the IF Demodulator
Section to select detection mode, bandwidth and gain. Refer to Figure 3-29, IF
Interface Block Diagram, as an aid in understanding the following description. Figure
6-30, IF Interface Schematic Diagram, may be referred to for greater component level
detail, if desired. The IF Interface consists of the following major circuit areas:
o Bus Transceiver
0
Address Latch
0
Address Decoder
0
RF Gain D/A
0
A/D Converter
0
Mode Latches
0
Audio Switching
3.4.22.1 Bus Transceiver
Transceiver U20 consists of 16 high speed buffer drivers, eight of which
are enabled at a time. The direction of data flow is controlled by the DIR and is
connected to the RD line. When RD is low, data flows through U20 to the
microprocessor. When RD is high, data flows through U20 from the microprocessor to
the bus.
3.4.22.2 Address Latch
Address latch U8 is an octal flip-flop. Data inputs to U8 are the low
address lines from U18. When ALE is low, indicating a valid address on the bus, the
clock inputs to U8 are strobed. The address bits on the D inputs of U8 are clocked to
the Q outputs. These outputs remain latched onto the address bus until the next ALE
cycle.
3-60