Watkins-Johnson Company WJ-8718-19/FE Instruction Manual page 148

WJ-8718-19/FE HF RECEIVER CIRCUIT DESCRIPTION
3.4.24 SERIAL I/O BUFFER (A6A4) (794300-1)
The Serial I/O Buffer mounts on thre A6 Motherboard (see paragraph
3.3.6). Refer to Figure 3-31, Serial I/O Buffer Block Diagram, as an aid in
understanding the following description. Figure 6-32, Serial I/O Buffer Schematic
Diagram, may be referred to for greater component level detail, if desired. The Serial
I/O Buffer consists of the following major circuit areas:
o D/A Converter, U6, U7, U8
o Address Decoder, U5
o Sync Serial I/O Buffers, U1-U3
3.4.24.1 D/A Converter, U6, U7, U8
U8 is a fixed voltage regulator producing a fixed +5 Vdc output from the
+15 Vdc supply input. The +5 Vdc is buffered by U7A and supplied to D/A reference
input at U6-2.
U6 is an 8-bit digital to analog converter. It takes an 8-bit digital input
from the address/data bus (equivalent analog range from 0 to 255) and converts it to
an analog voltage output with a range of 0 to 1.2 ma (full scale). The D/A is enabled
from decoder U5 via pin U6-2. U7B converts the current output of U6 to a voltage
range of 0 to +5 Vdc. The U7B output is sent to the Frequency Extender as the
preselector tuning voltage.
3.4.24.2 Address Decoder, U5
U5 is a 3-8 decoder driven by 2 bits on the address/bus. Outputs Y2, Y3
and Y4 are enabled by the input bits as follows:
INPUT BITS
A0 Al
H L
L H
H H
OUTPUT BITS
Y2 Y3 Y4
L H H
H L H
H H L
U5 is not clock enabled. Thus, any bits appearing on the A0 and Al
input of U5 are immediately decoded.
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