Watkins-Johnson Company WJ-8718-19/FE Instruction Manual page 134

WJ-8718-19/FE HF RECEIVER CIRCUIT DESCRIPTION
3.4.18.2.3 1st LO Terminal Count Detector
The terminal counts of both the swallow counter and the programmable
counter are detected by the terminal count control IC, U3. The prescaler mode is
controlled by the swallow counter logic outputs applied to the Z inputs of U3. The
terminal count for the swallow counter occurs at 09. The terminal count of the
programmable (main) counter is obtained when the correct logic levels are applied to
the P and B inputs of U3. As previously stated, the terminal count occurs at 370.
When the terminal count logic conditions are satisfied (at the P and B
inputs) U3 counts one clock pulse, then drops the FQ output line low. This resets the
flip-flops and presets (loads) the counters. At the end of the second clock pulse, the
Fn output goes high, starting the count cycle and clocking the VCO phase detector,
U5. The F0 output pulse to the phase detector is approximately
ay 40 kHz.
3.4.18.2.4 1st LO Phase Detector
Phase detector U5 receives a fixed 40 kHz reference frequency at the R
input and a variable frequency at the V input from the programmable divider. The
output of U5 consists of narrow pulses, whose average dc level is proportional to the
frequency difference between the V and R inputs.
When properly locked, the output pulses from U5 will be extremely narrow.
For large differences in frequency, the U5 output consists of wide pulses. These
pulses are integrated and amplified by the charge pump, U6C, and the loop filter, U7.
The resulting dc level is the VCO tuning voltage which drives the VCO frequency
determining network, thus controlling the VCO frequency.
3.4.18.2.4 3rd LO Synthesizer
The 3rd LO is part of the 1st and 3rd LO/Time Base board. The 3rd LO
has an input of two reference frequencies from the Time Base and a fixed outDut
frequency of 11.155 MHz.
VCXO (voltage-controlled crystal oscillator) for this synthesizer is formed
by Q8, Yl, CR7, and their associated components. The oscillator is crystal-controlled
to 11.155 MHz, with actual oscillating frequency determined by the dc tuning voltage
applied to CR7. The oscillator signal is buffered by follower Q9 and is split into two
signal paths. One path is to board pin A55, the 3rd LO output. The other path is
through sine-to-TTL converter Q10 to flip-flop U21B, which acts as a digital mixer.
The 3rd LO signal is compared to a 50 kHz reference at pin 11 of U21B, to produce a
5 kHz output, when the 3rd LO is locked. The 5 kHz output is the difference between
the VCO frequency (11.155 MHz) and the frequency that is the nearest integral
multiple of the clock frequency (223 x 50 kHz = 11.15 MHz). This 5 kHz signal from
the mixer is compared to a 5 kHz signal from the time base, via divide- by-2 U21A in
the phase detector, U22A. The charge pump U22B converts the differences in phase
and/or frequency into positive and negative going dc levels. These levels pass through
niter U22C and bias varactor diode CR7. The 11.155 MHz crystal oscillator is then
driven in the direction to achieve lock. The 3rd LO frequency then passes through
buffer amplifier Q9 and TTL driver Q10 to complete the loop.
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