Watkins-Johnson Company WJ-8718-19/FE Instruction Manual page 137

CIRCUIT DESCRIPTION WJ-8718-19/FE HF RECEIVER
o 32 MHz Fixed Loop
o Programmable Loop
o Output Loop
3.4.19.1 32 MHz Fixed Loop
The 32 MHz loop consists of VCO Q5 operating at approximately 32 MHz.
The frequency of Q5 is determined by varactor diode CR3. The Q5 output is amplified
by buffer Ql and drives a divide-by-32 counter U2/U3A. The resulting 1 MHz output
from the counter drives the V input of phase detector Ul. The R input of Ul is
driven by a 1 MHz reference signal from A5A1. The R and V inputs are compared by
UlA and the resulting dc output from loop filter UIB drives varactor diode CR3. The
dc voltage applied to CR3 locks the oscillating frequency of Q5 at exactly 32 MHz
The 32 MHz output from buffer Ql passes through filter C9/L9 and drives the input to
mixer U4.
3.4.19.2 Programmable Loop
The programmable loop consists of a prescaler, main programmable counter
phase detector, filter and VCO. The VCO, Q7, oscillates at approximately 200-210
MHz. The frequency of Q7 is determined by varactor diode CR5. The output of Q5
1nves the prescaler U14/U15. The prescaler has divide ratios of 100/101 and is under
che control of the swallow counter portion (U7/U8) of the main programmable counter
The purpose of the prescaler is to divide the 200 MHz VCO frequency down to a
frequency which can be handled by the main counter.
The main programmable counter consists of swallow counter U7/U8 and
main counter, U9/U10. U11A,B,C,D is wired as a terminal count detector'the swallow
counter and the main counter. The terminal count detector resets the main
programmable counter with a reset pulse when a terminal count of 24200 is reached
The swallow counter is preset with BCD digits from 00 to 99 and the main counter is
preset with BCD digits from 0 to 9 from the Digital Control Section. Counter U10 is
always wired to add binary 32 to the main counter preset, so the overall chain is
preset with the range of 3200 (3200 + 000) to 4199 (3200 + 999).
Suppose 000 is loaded into the 2nd LO. The input to the counters is 3200
+ 000 - 3200. The terminal count is 24200, so the divide ratio is 24200 - 3200 =
21000. Suppose 999 is loaded. The input is 3200 + 999 = 4199. The divide ratio is
24200 - 4199 = 20001. Suppose 500 is loaded. The input is 3200 + 500 = 3700 The
divide ratio is 24200 - 3700 = 20500.
The result pulse from Ull is approximately 10 kHz and drives the V input
tl P /Ai temo°I 12' The R inpUt of U12 is driven ^ the 10 kHz reference signal
from A5A1. U12A compares the R and V inputs and the resulting dc level is filtered
and amplified by loop filter U12B. The dc tuning voltage from U12B is applied to
varactor CR5. This tuning voltage locks the frequency of VCO Q7 to 200.01 MHz (999
^finL\nPU Th" viXde r-ati° =2°001) t0 210-°° MHz (00° preset inPuts or divide rati0
21000). The VCO output passes through the divide-by-1000 counter U16, U17 and
U19. The resulting output of 210.00 kHz to 200.01 kHz drives phase detector U6A.
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