Watkins-Johnson Company WJ-8718-19/FE Instruction Manual page 129

CIRCUIT DESCRIPTION WJ-8718-19/FE HF RECEIVER
3.4.18 1ST AND 3RD LO SYNTHESIZER/TIME BASE (A5A1) (791630)
The 1st and 3rd LO Synthesizer/Time Base Assembly mounts on the A5
Motherboard (see paragraph 3.3.5), and consists of two subassemblies: VCO, A5A1A1
and 1st & 3rd LO/Time Base, A5A1A2.
3.4.18.1 VCO (A5A1A1) (791629)
Refer to Figure 3-23, 1st LO Synthesizer Block Diagram, and Figure 6-24,
1st LO/VCO Assembly Schematic Diagram, as aids in understanding the following
description. The VCO has two inputs and two outputs. The inputs to the VCO are a
tuning voltage and a band-switching code. The VCO operates at a frequency four
times the desired 1st LO frequency. The band select code and the tuning voltage
combine to tune the oscillator from 171.64 MHz to 291.60 MHz in 40 kHz steps.
Octal encoder U13 accepts BCD inputs from the two MSD's of the 1st LO
frequency word from the Digital Control Section. U13 output consists of a binary
coded word Y2,Y3 and Y4. The levels for each bit are -12 V for logic 0 and +15 V for
logic 1. Applying a negative-true-code voltage to the BAND SELECT inputs tunes the
oscillator to one of eight different frequency bands. When the BAND SELECT inputs
are all positive, CR1 through CR3 are off, and L2 through L4 are effectively out of
the circuit. This allows the inductance of Tl to be maximum. When any or all of the
BAND SELECT inputs are negative, the corresponding diode will conduct and the
inductance of Tl will be reduced by the shunting effect of the inductor (L2, L3 or
'A).
Varactor diode CR4 fine tunes the oscillator in response to the tuning
voltage input. Common-emitter amplifier Q2 keeps load changes at the input of power
divider R9 and RIO from being reflected back to the output of oscillator Ql. T2
matches the output of the amplifier to the input of the power divider. The signal is
coupled to buffer amplifier Q3, which drives the prescaler of the synthesizer. R9 and
C15 couple the signal from Q2 to the input of the divide-by-4 circuit Ul. MECL
divider Ul divides the signal frequency by four and amplifier Q5 isolates its output
from load changes. Voltage regulator Q4 provides Ul and Q5 with a -7.0 V power
input from the -12 V power supply input to the assembly. Amplifiers Q5 and Q7
provide the relatively high currents needed to drive the input of the 1st Mixer.
3.4.18.2 1st and 3rd LO/Time Base (A5A1A2) (791600)
Refer to Figure 3-23, 1st LO Synthesizer Block Diagram, Figure 3-24, 3rd
LO Block Diagram, and Figure 3-25, Time Base Block Diagram, as aids in understanding
the following description. Figure 6-23, 1st and 3rd LO Synthesizer/Time Base
Schematic Diagram, Figure 6-24, 1st LO/VCO Schematic Diagram,and Figure 6-25, 1st
and 3rd Synthesizer Schematic Diagram, may be referred to for greater component level
detail, if desired. The 1st and 3rd LO/Time Base consists of the following major
circuit areas:
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