Asynchronous I/O Block Diagram - Watkins-Johnson Company WJ-8718-19/FE Instruction Manual

CIRCUIT DESCRIPTION WJ-8718-19/FE HF RECEIVER
3.4.22.3 Address Decoder
Address decoder Ull is a 3-to-8 octal decoder. When addressed by applying
a high input to Gl and a low to inputs G2A and G2B, this decoder provides a logic low
output on one of eight Y outputs. Ull is addressed by bits A0-A2 and its Y outputs
are tied to enable inputs of read only and write only devices on the board.
3.4.22.4 RF Gain D/A
D/A converter U23 is used when the receiver is under remote control. An
8-bit binary coded RF gain word is latched into its inputs when the WR1 input is
pulsed low during a WR cycle from the Y3 output of Ull. U23 provides a current
output which is converted to positive voltage by U23. Each binary input bit
corresponds to 0.019 Vdc at the output of U23.
3.4.22.5 A/D Converter
A/D converter U25 consists of an eight channel multiplexed analog switch,
an 8-bit A/D converter, address decoder and tri-state output buffer. Seven of the
eight channel inputs to the multiplexer are connected to receiver signals and are
monitored during receiver operation. Channel inputs are selected by a 3-bit binary
address on the A,B and C inputs. Converted data is read from the output buffer via
the Y4 output of Ull which enables the output buffer of U25.
U25 is a successive approximation converter with an input voltage range of
0 to +5 Vdc. Each output bit from the buffer corresponds to an input of 0.019 Vdc.
3.4.22.6 Mode Latches
Three registers (U5, U9, U21) serve as storage devices for control of the
IF Demodulator Section. Each register latches the data on its D inputs to the Q
outputs on a positive-going transition of its clock pulse. The registers are selected by
the Y0-Y4 outputs of Ull. U5 controls bandwidth selection, U9 controls gain/detection
mode selection and U21 controls local/remote selection.
3.4.23 ASYNCHRONOUS I/O (A6A3) (796037)
The Asynchronous I/O mounts on the I/O Motherboard, A6 (see paragraph
3.3.6). The Asynchronous I/O interfaces the Digital Control microprocessor with the IF
Demodulator Section to select detection mode, bandwidth and gain. Refer to
Figure 3-30, Asynchronous I/O Block Diagram, as an aid in understanding the following
description. Figure 6-31, Asynchronous I/O Schematic Diagram, may be referred to for
greater component level detail, if desired. The Asynchronous I/O consists of the
following major circuit areas:
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