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CIRCUIT DESCRIPTION
WJ-8718-19/FE HF RECEIVER
3.4.10.2
Second Mixer (A3A2) (370646)
Signals passed by A1FL1 are coupled to-a second amplifier, A2Q2, through
a coupling network. This amplifier is biased by constant current source A2Q1 biasing
network.
Its output circuit is a broadly tuned transformer, but is shunted by gain
control diode A2CR2.
As the current through the diode increases, its RF impedance
decreases and the net gain of A2Q2 is decreased. Current to A2CR2 is supplied by the
RF Gain portion of the AGC, A4A6.
As the current varies from zero to maximum
there is approximately 30 dB of gain reduction.
The output signal of A2Q2 is down converted by the 2nd Mixer, A2U1.
The 2nd LO signal enters the Input Converter via A2J1 at a level of approximately
0 dBm. Common emitter amplifiers, A2Q5 and A2Q6, provide enough gain to bring the
2nd LO signal to a nominal level of +17 dBm. Each of these stages is broadly tuned
transformer-coupled and each has some unbypassed emitter resistance to preserve a
relatively low harmonic content in the 2nd LO signal.
The 2nd Mixer is followed by a bipolar cascode amplifier.
It consists of
common emitter stage A2Q4 and common base stage A2Q3. These provide relatively
high gain with good stability and low noise contribution. The 2nd IF signal is coupled
from the collector of A2Q3 through Matching Network Zl. Zl consists of a single pole
bandpass filter CI, C2, CI and C2, and has a center frequency of 10.7 MHz.
The
output of Zl passes through A2J3 to rear panel WB OUT J16.
Transformer A2T2
couples the 2nd IF output of A2Q3 to crystal filter A2FL1.
This filter has a center
frequency of 10.7 MHz, a bandwidth of 50 kHz, and requires 50 ohm terminations.
The amplified, bandlimited 2nd IF output from A3 drives the 50 ohm input
to the 10.7 MHz Filter Switch, A4A1.
3.4.11
10.7 MHz FILTER SWITCH (A4A1) (791594)
The 10.7 MHz Filter Switch mounts on the IF Motherboard, A4 (see
paragraph 3.3. 4 ) . Figure 3-16 is a detailed functional block diagram of the 10.7 MHz
Filter Switch which should be referred to in the following circuit description. Figure
6-15, 10.7 MHz Filter Switch Schematic Diagram, may be referred to for greater
component level detail, if desired.
The 10.7 MHz Filter Switch receives the 10.7 MHz IF signal output from
the Input Converter, A3. At this point, the IF bandwidth has been set at 100 kHz by
a filter in the Input Converter. The 10.7 MHz Filter Switch contains bandpass filters
of 6.0 kHz and 3.2 kHz bandwidth.
The purpose of this circuit is to route the IF
signal through one of these filters, or through a wideband path which allows the full
50 kHz bandwidth to pass. The selection of the filter path is made by application of a
logic high level to one of the three control terminals.
In any IF bandwidth, a logic high is applied to one of three control lines
from the I/O Motherboard, at pin 15, 17, or 19.
These lines are connected to the
non-inverting inputs of U1A, U1B, and U2A.
The inverting inputs are held at
approximately 0.8 V by voltage divider R52-R53. The output voltage of the selected
rp-amp swings positive, turning on one pair of common-emitter IF amplifier stages,
or example, if U1A is selected, Ql and Q4 are turned on.
3-32
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