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WJ-8718-19/FE HF RECEIVER
CIRCUIT DESCRIPTION
The microprocessor provides RD, WR and ALE outputs for bus control and
RST inputs for interrupts.
Clock generator Ull drives the microprocessor at 2 MHz.
During power up, U11A and U11F provide a time-delayed reset function which holds
the microprocessor from initializing until the power supply circuits have stabilized.
3.4.21.2
Bi-Directional Bus Transceiver
Transceiver U4 consists of 16 high speed buffer drivers, eight of which are
enabled at a time.
The direction of data flow is controlled by the DIR and is
connected to the RD line.
When RD is low, data flows through U4 to the
microprocessor.
When RD is high, data flows through U4 from the microprocessor to
the bus.
3.4.21.3
Address Latch
Address latch U5/U6 are octal flip-flops.
Data inputs to U5 and U6 are
the low and high order address lines from U18.
When ALE is low, indicating a valid
address on the bus, the clock inputs to U5 and U6 are strobed.
The address bits on
the D inputs of U5 and U6 are clocked to the Q outputs.
These outputs remain
latched onto the address bus until the next ALE cycle.
3.4.21.4
Address Decoder
Address decoders U7 and U8 are 3-to-8 octal decoders. When addressed by
applying a high input to Gl and a low to inputs G2A and G2B, these decoders provide
a logic low output on one of eight Y outputs. U7 is addressed by bits A12-A15 and its
Y0-Y4 outputs are enabled for ROM 1, U8-G2B, RAM and ROM 2. U8 is addressed by
bits A0-A2,A4 and A5, and its Y0-Y5 outputs are clock strobes used to latch bus data
into the frequency registers.
3.4.21.5
Memory
Memory consists of RAM, U3, and ROM, Ul and U2.
The RAM is a 2K by
8 CMOS integrated circuit.
RAM stores data and current receiver status.
RAM is
enabled by the CE input from decoder U7. When selected, CE goes low, selecting the
RAM chip. RAM read and write inputs are connected to the RD and WR outputs from
the microprocessor.
RD is low when reading data from the RAM to the bus.
WR is
low when writing data from the bus to the RAM.
The ROM consists of two 8K by 8 CMOS EPROM's.
The ROM contains the
operating software for the receiver Digital Control Section. Ul and U2 are selected by
CE inputs from decoder U7.
The OE inputs are tied to the RD line from the
microprocessor.
During a ROM read cycle, CE and OE inputs are both pulled low.
3-59
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