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19.2 Transmit
TRANSMIT SIDE TIMING Figure 19-7
FRAME#
14 15 16
1
TSYNC
TSSYNC
2
TSYNC
3
TLCLK
3
TLINK
Notes:
1. TSYNC in frame mode (TCR1.1 = 0)
2. TSYNC in multiframe mode (TCR1.1 = 1)
3. TLINK is programmed to source just the Sa4 bit
4. This diagram assumes both the CAS MF and the CRC4 MF begin with the TAF frame
5. TLINK and TLCLK are not synchronous with TSSYNC
1 2 3 4 5
6 7 8 9 10
94 of 117
11 12
13 14 15 16 1 2 3 4 5
DS21354 & DS21554
6 7 8 9 10
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