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14.1 Hardware Scheme
On the receive side, all of the received data is reported at the RLINK pin. Via RCR2, the user can control
the RLCLK pin to pulse during any combination of Sa bits. This allows the user to create a clock that can
be used to capture the needed Sa bits. If RSYNC is programmed to output a frame boundary, it will
identify the Si bits. See Section 19.1 for detailed timing.
On the transmit side, the individual Sa bits can be either sourced from the internal TNAF register (see
Section 14.2 for details) or from the external TLINK pin. Via TCR2, the framer can be programmed to
source any combination of the additional bits from the TLINK pin. If the user wishes to pass the Sa bits
through the framer without them being altered, then the device should be set up to source all five Sa bits
via the TLINK pin and the TLINK pin should be tied to the TSER pin. Si bits can be inserted through the
TSER pin via the clearing of the TCR1.3 bit. Please see the timing diagrams and the transmit data flow
diagram in Section 19.2 for examples.
14.2 Internal Register Scheme Based On Double–Frame
On the receive side, the RAF and RNAF registers will always report the data as it received in the
Additional and International bit locations. The RAF and RNAF registers are updated with the setting of
the Receive Align Frame bit in Status Register 2 (SR2.6). The host can use the SR2.6 bit to know when to
read the RAF and RNAF registers. It has 250 us to retrieve the data before it is lost.
On the transmit side, data is sampled from the TAF and TNAF registers with the setting of the Transmit
Align Frame bit in Status Register 2 (SR2.3). The host can use the SR2.3 bit to know when to update the
TAF and TNAF registers. It has 250 us to update the data or else the old data will be retransmitted. Data
in the Si bit position will be overwritten if either the framer is programmed: (1) to source the Si bits from
the TSER pin, (2) in the CRC4 mode, or (3) have automatic E–bit insertion enabled. Data in the Sa bit
position will be overwritten if any of the TCR2.3 to TCR2.7 bits are set to one (please see Section 14.1
for details). Please see the register descriptions for TCR1 and TCR2 and Figure 19-15 for more details.
RAF: RECEIVE ALIGN FRAME REGISTER (Address=2F Hex)
(MSB)
Si
0
SYMBOL
POSITION NAME AND DESCRIPTION
Si
RAF.7
0
RAF.6
0
RAF.5
1
RAF.4
1
RAF.3
0
RAF.2
1
RAF.1
1
RAF.0
0
1
International Bit.
Frame Alignment Signal Bit.
Frame Alignment Signal Bit.
Frame Alignment Signal Bit.
Frame Alignment Signal Bit.
Frame Alignment Signal Bit.
Frame Alignment Signal Bit.
Frame Alignment Signal Bit.
57 of 117
1
0
DS21354 & DS21554
(LSB)
1
1
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