Test Registers - Dallas Semiconductor DS21354L Manual

17.4 Test Registers

IEEE 1149.1 requires a minimum of two test registers; the bypass register and the boundary scan register.
An optional test register has been included with the DS21354/554 design. This test register is the
identification register and is used in conjunction with the IDCODE instruction and the Test-Logic-Reset
state of the TAP controller.
Boundary Scan Register
This register contains both a shift register path and a latched parallel output for all control cells and
digital I/O cells and is n bits in length. See Table 17-4 for all of the cell bit locations and definitions.
Bypass Register
This is a single one-bit shift register used in conjunction with the BYPASS, CLAMP, and HIGHZ
instructions which provides a short path between JTDI and JTDO.
Identification Register
The identification register contains a 32-bit shift register and a 32-bit latched parallel output. This
register is selected during the IDCODE instruction and when the TAP controller is in the Test-Logic-
Reset state. See Table 17-3 and Table 17-4 for more information on bit usage.
BOUNDARY SCAN CONTROL BITS Table 17-4
BIT
2
1
0
72
71
70
69
68
67
66
PIN SYMBOL
1 RCHBLK
2 JTMS
3 8MCLK
4 JTCLK
5 JTRST
6 RCL
7 JTDI
8 N/C
9 N/C
10 JTDO
11 BTS
12 LIUC
13 8XCLK
14 TEST
15 NC
16 RTIP
17 RRING
18 RVDD
19 RVSS
20 RVSS
21 MCLK
22 XTALD
23 NC
24 RVSS
25 INT
26 N/C
TYPE CONTROL BIT DESCRIPTION
O
I
O
I
I
O
I
–
–
O
I
I
O
I
–
I
I
–
–
–
I
O
–
–
O
–
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DS21354 & DS21554