Jtag Test Access Port Pins - Dallas Semiconductor DS21354L Manual

Signal Name:
Signal Description:
Signal Type:
In non–multiplexed bus operation (MUX = 0), serves as the upper address bit. In multiplexed bus
operation (MUX = 1), serves to de-multiplex the bus on a positive–going edge.
Signal Name:
Signal Description:
Signal Type:
WR* is an active low signal.

4.1.4 JTAG Test Access Port Pins

Signal Name:
Signal Description:
Signal Type:
This signal is used to asynchronously reset the test access port controller. At power up, JTRST* must be
toggled from low to high. This action will set the device into JTAG DEVICE ID mode enabling the test
access port features. This pin has a 10k pull up resistor. When FMS=1, this pin is tied low internally.
Tie JTRST* low if JTAG is not used and the framer is in DS21352/552 mode (FMS low).
Signal Name:
Signal Description:
Signal Type:
This pin is sampled on the rising edge of JTCLK and is used to place the test access port into the various
defined IEEE 1149.1 states. This pin has a 10k pull up resistor.
Signal Name:
Signal Description:
Signal Type:
This signal is used to shift data into JTDI on the rising edge and out of JTDO on the falling edge.
Signal Name:
Signal Description:
Signal Type:
Test instructions and data are clocked into this pin on the rising edge of JTCLK. This pin has a 10k pull
up resistor.
Signal Name:
Signal Description:
Signal Type:
Test instructions and data are clocked out of this pin on the falling edge of JTCLK. If not used, this pin
should be left unconnected.
ALE(AS)/a7
Address Latch Enable(Address Strobe) or A7
Input
WR*(R/W*)
Write Input(Read/Write)
Input
JTRST*
IEEE 1149.1 Test Reset
Input
JTMS
IEEE 1149.1 Test Mode Select
Input
JTCLK
IEEE 1149.1 Test Clock Signal
Input
JTDI
IEEE 1149.1 Test Data Input
Input
JTDO
IEEE 1149.1 Test Data Output
Output
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DS21354 & DS21554