Functional Timing Diagrams; Receive - Dallas Semiconductor DS21354L Manual

19 FUNCTIONAL TIMING DIAGRAMS

19.1 Receive

RECEIVE SIDE TIMING Figure 19-1
FRAM E#
RFSYNC
1
RSYNC
2
RSYNC
3
RLCLK
4
RLINK
Notes:
1. RSYNC in frame mode (RCR1.6 = 0)
2. RSYNC in multiframe mode (RCR1.6 = 1)
3. RLCLK is programmed to output just the Sa bits
4. RLINK will always output all 5 Sa bits as well as the rest of the receive data stream
5. This diagram assumes the CAS MF begins in the RAF frame
1
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1
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DS21354 & DS21554