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SYMBOL
POSITION NAME AND DESCRIPTION
JAS
LICR.3
JABDS
LICR.2
DJA
LICR.1
TPD
LICR.0
16.1 Receive Clock And Data Recovery
The DS21354/554 contains a digital clock recovery system. See Figure 3-1 and Figure 16-1 for more
details. The device couples to the receive E1 shielded twisted pair or COAX via a 1:1 transformer. See
Table 16-3 for transformer details. The 2.048 MHz clock attached at the MCLK pin is internally
multiplied by 16 via an internal PLL and fed to the clock recovery system. The clock recovery system
uses the clock from the PLL circuit to form a 16 times over-sampler which is used to recover the clock
and data. This over-sampling technique offers outstanding jitter tolerance (see Figure 16-3).
Normally, the clock that is output at the RCLKO pin is the recovered clock from the E1 AMI/HDB3
waveform presented at the RTIP and RRING inputs. When no AMI signal is present at RTIP and RRING,
a Receive Carrier Loss (RCL) condition will occur and the RCLKO will be sourced from the clock
applied at the MCLK pin. If the jitter attenuator is either placed in the transmit path or is disabled, the
RCLKO output can exhibit slightly shorter high cycles of the clock. This is due to the highly over-
sampled digital clock recovery circuitry. If the jitter attenuator is placed in the receive path (as is the case
in most applications), the jitter attenuator restores the RCLK to being close to 50% duty cycle. Please see
the Receive AC Timing Characteristics in Section 21.3 for more details.
16.2 Transmit Waveshaping And Line Driving
The DS21354/554 uses a set of laser–trimmed delay lines along with a precision Digital–to–Analog
Converter (DAC) to create the waveforms that are transmitted onto the E1 line. The waveforms meet the
ITU G.703 specifications. See Figure 16-5.
The user will select which waveform is to be generated by properly programming the L2/L1/L0 bits in the
Line Interface Control Register (LICR). The DS21354/554 can set up in a number of various
configurations depending on the application. See tables below and Figure 16-5.
Jitter Attenuator Select.
0 = place the jitter attenuator on the receive side
1 = place the jitter attenuator on the transmit side
Jitter Attenuator Buffer Depth Select.
0 = 128 bits
1 = 32 bits (use for delay sensitive applications)
Disable Jitter Attenuator.
0 = jitter attenuator enabled
1 = jitter attenuator disabled
Transmit Power Down.
0 = normal transmitter operation
1 = powers down the transmitter and 3-states the TTIP and TRING pins
69 of 117
DS21354 & DS21554
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