Parallel Control Port Pins - Dallas Semiconductor DS21354L Manual

Signal Name:
Signal Description:
Signal Type:
An 8.192MHz clock output that is referenced to the clock that is output at the RCLK pin.
Signal Name:
Signal Description:
Signal Type:
Updated on the rising edge of RCLKO with bipolar data out of the line interface. This pin is normally
tied to RPOSI.
Signal Name:
Signal Description:
Signal Type:
Updated on the rising edge of RCLKO with the bipolar data out of the line interface. This pin is normally
tied to RPOSI.
Signal Name:
Signal Description:
Signal Type:
Buffered recovered clock from the T1 line. This pin is normally tied to RCLKI.
Signal Name:
Signal Description:
Signal Type:
Sampled on the falling edge of RCLKI for data to be clocked through the receive side framer. RPOSI and
RNEGI can be tied together for a NRZ interface. Can be internally connected to RPOSO by tying the
LIUC pin high.
Signal Name:
Signal Description:
Signal Type:
Sampled on the falling edge of RCLKI for data to be clocked through the receive side framer. RPOSI and
RNEGI can be tied together for a NRZ interface. Can be internally connected to RNEGO by tying the
LIUC pin high.
Signal Name:
Signal Description:
Signal Type:
Clock used to clock data through the receive side framer. This pin is normally tied to RCLKO. Can be
internally connected to RCLKO by tying the LIUC pin high.

4.1.3 Parallel Control Port Pins

Signal Name:
Signal Description:
Signal Type:
Flags host controller during conditions and change of conditions defined in the Status Registers 1 and 2
and the HDLC Status Register. Active low, open drain output
8MCLK
8 MHz Clock
Output
RPOSO
Receive Positive Data Input
Output
RNEGO
Receive Negative Data Input
Output
RCLKO
Receive Clock Output
Output
RPOSI
Receive Positive Data Input
Input
RNEGI
Receive Negative Data Input
Input
RCLKI
Receive Clock Input
Input
INT*
Interrupt
Output
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DS21354 & DS21554