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TCBR1/TCBR2/TCBR3/TCBR4: DEFINITION WHEN CCR3.6=1
(MSB)
CH18
CH3
CH22
CH7
CH26
CH11
CH30
CH15
* these bits should be set to one to allow the internal TS1 register to create the CAS Multiframe
Alignment Word and Spare/Remote Alarm bits.
The user can also take advantage of this functionality to intermix signaling data from the TSIG pin and
from the internal Transmit Signaling Registers (TS1 to TS16). As an example, assume that the user
wishes to source all the signaling data except for voice channels 5 and 10 from the TSIG pin. In this
application, the following bits and registers would be programmed as follows:
CONTROL BITS
THSE = 1 (CCR3.2)
TCBFS = 1 (CCR3.6)
T16S = 0 (TCR1.5)
11 PER–CHANNEL CODE GENERATION AND LOOPBACK
The DS21354/554 can replace data on a channel–by–channel basis in both the transmit and receive
directions. The transmit direction is from the backplane to the E1 line and is covered in Section 11.1. The
receive direction is from the E1 line to the backplane and is covered in Section 11.2.
11.1 Transmit Side Code Generation
In the transmit direction there are two methods by which channel data from the backplane can be
overwritten with data generated by the framer. The first method which is covered in Section 11.1.1 was a
feature contained in the original DS2153 while the second method which is covered in 11.1.2 is a new
feature of the DS2154/354/554.
11.1.1 Simple Idle Code Insertion and Per–Channel Loopback
The first method involves using the Transmit Idle Registers (TIR1/2/3/4) to determine which of the 32 E1
channels should be overwritten with the code placed in the Transmit Idle Definition Register (TIDR).
This method allows the same 8–bit code to be placed into any of the 32 E1 channels. If this method is
used, then the CCR3.5 control bit must be set to zero.
Each of the bit position in the Transmit Idle Registers (TIR1/TIR2/TIR3/TIR4) represent a DS0 channel
in the outgoing frame. When these bits are set to a one, the corresponding channel will transmit the Idle
Code contained in the Transmit Idle Definition Register (TIDR).
The Transmit Idle Registers (TIRs) have an alternate function that allow them to define a Per–Channel
LoopBack (PCLB). If the TIRFS control bit (CCR3.5) is set to one, then the TIRs will determine which
channels (if any) from the backplane should be replaced with the data from the receive side or in other
words, off of the E1 line. If this mode is enabled, then transmit and receive clocks and frame syncs must
be synchronized.
CH17
CH2
CH21
CH6
CH25
CH10
CH29
CH14
REGISTER VALUES
TS1 = 0Bh (MF alignment word, remote alarm etc.)
TCBR1 = 03h (source timeslot 16, frame 1 data)
TCBR2 = 01h (source voice Channel 5 signaling data from TS6)
CBR3 = 04h (source voice Channel 10 signaling data from TS11)
TCBR4 = 00h
CH16
CH1
CH20
CH5
CH24
CH9
CH28
CH13
52 of 117
DS21354 & DS21554
(LSB)
1*
1*
CH19
CH4
CH23
CH8
CH27
CH12
TCBR1(22)
TCBR2(23)
TCBR3(24)
TCBR4(25)
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