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One method to accomplish this would be to tie RCLK to TCLK and RFSYNC to TSYNC. There are no
restrictions on which channels can be looped back or on how many channels can be looped back.
TIR1/TIR2/TIR3: TRANSMIT IDLE REGISTERS (Address=26 to 29 Hex)
[Also used for Per–Channel Loopback]
(MSB)
CH8
CH7
CH16
CH15
CH24
CH23
CH32
CH31
SYMBOLS
POSITIONS NAME AND DESCRIPTION
CH1 - 32
TIR1.0 - 4.7
NOTE:
If CCR3.5 = 1, then a zero in the TIRs implies that channel data is to be sourced from TSER and a one
implies that channel data is to be sourced from the output of the receive side framer (i.e., Per–Channel
Loopback; see Figure 3-1).
TIDR: TRANSMIT IDLE DEFINITION REGISTER (Address=2A Hex)
(MSB)
TIDR7
TIDR6
SYMBOL
POSITION NAME AND DESCRIPTION
TIDR7
TIDR.7
TIDR0
TIDR.0
11.1.2 Per–Channel Code Insertion
The second method involves using the Transmit Channel Control Registers (TCC1/2/3/4) to determine
which of the 32 E1 channels should be overwritten with the code placed in the Transmit Channel
Registers (TC1 to TC32). This method is more flexible than the first in that it allows a different 8–bit
code to be placed into each of the 32 E1 channels.
TC1 TO TC32: TRANSMIT CHANNEL REGISTERS (Address=60 to 7F Hex)
(for brevity, only channel one is shown; see for other register address)
(MSB)
C7
C6
SYMBOL
POSITION NAME AND DESCRIPTION
C7
TC1.7
C0
TC1.0
CH6
CH5
CH14
CH13
CH22
CH21
CH30
CH29
Transmit Idle Code Insertion Control Bits.
0 = do not insert the Idle Code in the TIDR into this channel
1 = insert the Idle Code in the TIDR into this channel
TIDR5
TIDR4
MSB of the Idle Code (this bit is transmitted first)
LSB of the Idle Code (this bit is transmitted last)
C5
C4
MSB of the Code (this bit is transmitted first)
LSB of the Code (this bit is transmitted last)
CH4
CH3
CH12
CH11
CH20
CH19
CH28
CH27
TIDR3
C3
C2
53 of 117
DS21354 & DS21554
(LSB)
CH2
CH1
CH10
CH9
CH18
CH17
CH26
CH25
TIDR2
TIDR1
(LSB)
C1
C0
TIR1 (26)
TIR2 (27)
TIR3 (28)
TIR4 (29)
(LSB)
TIDR0
TC1 (60)
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