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16.3 Jitter Attenuator
The DS21354/554 contains an onboard jitter attenuator that can be set to a depth of either 32 or 128 bits
via the JABDS bit in the Line Interface Control Register (LICR). The 128–bit mode is used in
applications where large excursions of wander are expected. The 32–bit mode is used in delay sensitive
applications. The characteristics of the attenuation are shown in Figure 16-3. The jitter attenuator can be
placed in either the receive path or the transmit path by appropriately setting or clearing the JAS bit in the
LICR. Also, the jitter attenuator can be disabled (in effect, removed) by setting the DJA bit in the LICR.
In order for the jitter attenuator to operate properly, a 2.048 MHz clock (+/-50 ppm) must be applied at
the MCLK pin or a crystal with similar characteristics must be applied across the MCLK and XTALD
pins. If a crystal is applied across the MCLK and XTALD pins, then the maximum effective series
resistance should be 30 ohms and capacitors should be placed from each leg of the crystal to ground as
shown in Figure 16-2. Onboard circuitry adjusts either the recovered clock from the clock/data recovery
block or the clock applied at the TCLKI pin to create a smooth jitter free clock which is used to clock
data out of the jitter attenuator FIFO. It is acceptable to provide a gapped/bursty clock at the TCLKI pin if
the jitter attenuator is placed on the transmit side. If the incoming jitter exceeds either 120 UIpp (buffer
depth is 128 bits) or 28 UIpp (buffer depth is 32 bits), then the DS21354/554 will divide the internal
nominal 32.768 MHz clock by either 15 or 17 instead of the normal 16 to keep the buffer from
overflowing. When the device divides by either 15 or 17, it also sets the Jitter Attenuator Limit Trip
(JALT) bit in the Receive Information Register (RIR.5).
BASIC EXTERNAL ANALOG CONNECTIONS Figure 16-1
E1 Transmit
Line
E1 Receive
Line
Notes:
All capacitors values are in uf.
10uf capacitor on TVDD is of tantalum construction.
See Table 16-1 and Table 16-2 for transformer selection.
0.47
(non-
polarized)
Rt
Rt
N : 1
(See Note 1)
1 : 1
Rr
Rr
0.1uF
71 of 117
DS21354 / 554
DVDD
TTIP
TRING
DVSS
RVDD
RVSS
TVDD
RTIP
TVSS
RRING
MCLK
DS21354 & DS21554
VDD
0.01
0.1
0.1
+
0.1
10
2.048MHz
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